Optimizing doping control in short channel MOS

Claim 1

An improved process for fabricating short channel metal oxide semiconductor devices comprising source and drain regions separated by gate regions, wherein the process of forming a shallow channel doping region includes forming said shallow channel doping region beneath the surface of a semiconductor, forming source-drain regions of opposite conductivity type on either side of said shallow doping region, forming a gate insulator on the surface of said semiconductor above said shallow channel doping region and extending over a portion of said source-drain region adjacent said shallow channel doping region, and forming a gate electrode to said gate oxide, the improved process including: (a) forming a doped glass layer on said substrate, said doped glass layer acting as a source of dopant to form said source-drain regions of opposite conductivity by subsequent diffusion into said silicon substrate at an elevated temperature; (b) forming an insulating layer on said doped glass layer; (c) patterning said insulating layer and said doped glass layer to form vertical structures which define said gate region, said vertical structures disposed on either side of said gate region; (d) forming an oxide coating on said insulating layer and on said vertical structures, said narrowed spacing between said vertical structures, said narrowed spacing being less than the distance separating said source and drain regions; (e) implanting ions through said oxide coating into said gate region to form said shallow channel doping region to thereby laterally space said shallow channel doping region by a distance S from said sidewalls of said vertical structures and to self-align said shallow channel doping region to said sourcedrain regions, said shallow channel doping region centered between said source-drain regions and separated therefrom; (f) anisotropically etching said oxide coating to leave said oxide coating on said sidewalls of said vertical structures to thereby form oxide spacers; (g) forming said gate insulator in said gate region; and (h) depositing said gate electrode.