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US5210870A
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Database sort and merge apparatus with multiple memory arrays having alternating access
Assignee: International Business Machines Corp
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Filing: 1990-03-27
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Granted: 1993-05-11
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Expires: 2010-03-27
Abstract
Abstract A processor functioning as a coprocessor attached to a central processing complex provides efficient execution of the functions required for database processing: sorting, merging, joining, searching and manipulating fields in a host memory system. The specialized functional units: a memory interface and field extractor/assembler, a Predicate Evaluator, a combined sort/merge/join unit, a hasher, and a microcoded control processor, are all centered around a partitioned Working Store. Each functional unit is pipelined and optimized according to the function it performs, and executes its portion of the query efficiently. All functional units execute simultaneously under the control processor to achieve the desired results. Many different database functions can be performed by chaining simple operations together. The processor can effectively replace the CPU bound portions of complex database operations with functions that run at the maximum memory access rate improving performance on complex queries.
Inventors
- 👤 Richard I. Baum
- 👤 Glen A. Brent
- 👤 Donald H. Gibson
- 👤 David B. Lindquist
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:30
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F16/00; G06F16/20; G06F16/28; G06F16/284; F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/027; Y; Y10; Y10S; Y10S707/00; Y10S707/99931; Y10S707/99933; Y10S707/99934; Y10S707/99937; Y10S707/99941; Y10S707/99943; Y10S707/99951; Y10S707/99952
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
261 words
An apparatus for sorting and merging a plurality of keys, comprising: first memory array means for storing the keys at respective memory addresses, the first memory array means having first and second addressable areas therein, the first and second addressable areas being independently and simultaneously accessible; second memory arrays means for storing the memory addresses of the keys; third memory array means for storing the memory addresses of the keys; write enable means for alternately reading and write enabling the second and third memory array means for reading and writing said addresses from one of said second and third memory array means to the other memory array means in alternating fashion for each sorting pass until said keys are sorted and merged; comparator means coupled with the first memory means, for comparing a first key from one of the first addressable areas with a second key from one of the second addressable areas; and control means, coupled with the first memory array means, the second memory array means, the third memory array means, the write enable means, the counter means, and the comparator means, for: reading first and second addresses of first and second ones of the keys from a non-write enabled one of the second and third memory means, causing addressing the first and second addressable areas of the first memory means with the first and second addresses for comparing said keys, and writing each winning key into the write-enabled one of the second and third memory array means, responsive to a comparison of the keys by the comparator means.
Claim 2
Independent Claim
261 words
An apparatus for sorting and merging a plurality of keys, comprising: first memory array means for storing the keys at respective memory addresses, the first memory array means having first and second addressable areas therein, the first and second addressable areas being independently and simultaneously accessible; second memory arrays means for storing the memory addresses of the keys; third memory array means for storing the memory addresses of the keys; write enable means for alternately reading and write enabling the second and third memory array means for reading and writing said addresses from one of said second and third memory array means to the other memory array means in alternating fashion for each sorting pass until said keys are sorted and merged; comparator means coupled with the first memory means, for comparing a first key from one of the first addressable areas with a second key from one of the second addressable areas; and control means, coupled with the first memory array means, the second memory array means, the third memory array means, the write enable means, the counter means, and the comparator means, for: reading first and second addresses of first and second ones of the keys from a non-write enabled one of the second and third memory means, causing addressing the first and second addressable areas of the first memory means with the first and second addresses for comparing said keys, and writing each winning key into the write-enabled one of the second and third memory array means, responsive to a comparison of the keys by the comparator means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-10 | 1996-11-09 | 1997-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-10 | 2000-11-09 | 2001-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-10 | 2004-11-09 | 2005-05-11 | $7700.00 | Window Closed / Lapsed |