Patent US5210841A successfully refreshed from Google Patents.
US5210841A
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External memory accessing system
Assignee: Advanced Micro Devices Inc
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Filing: 1990-01-30
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Granted: 1993-05-11
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Expires: 2010-01-30
Abstract
Abstract There is disclosed a new and improved external memory accessing system for use in a microprocessor. The system includes a physical address cache for storing a plurality of entries including register numbers and corresponding translated external memory address locations which were used for execution of previous load instructions. The system further includes means responsive to a current load instruction for determining if the address of the register specified in the load instruction is within the physical address cache and means for conveying to the external memory, at the beginning of the execution stage of the load instruction, a previously translated external memory physical address corresponding to a specified register stored in the physical address cache. Also disclosed is a new and improved address generator for generating a new translated external memory physical address which is conveyed to the external memory and to the physical address cache for updating the physical address cache.
Inventors
- 👤 William M. Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:56
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
353 words
In a processor of the type which processes instructions in serial stages including a fetch stage, a decode stage, an execute stage, and a write-back stage, and which includes an external memory for storing data to be executed upon, said external memory including a plurality of storage locations with each said location having a unique physical storage address, and wherein said processor further includes a first plurality of registers, each said first plurality of registers having a unique address and being arranged for storing an untranslated address corresponding to one of said external memory locations, and a second plurality of registers, each said second plurality of registers having a unique address and being arranged for storing data to be executed upon by said processor, and wherein the addresses stored in said first plurality of registers require translation to said physical external memory location addresses to permit said external memory locations to be accessed, a new and improved system for efficiently accessing the data stored in one of said external memory locations and providing said data to one of said second plurality of registers responsive to a currently fetched load instruction including the address of one of said first plurality of registers, said system comprising: a physical address cache for storing a plurality of entries including the addresses of said first plurality of registers and the corresponding translated external memory address locations for those ones of said first plurality registers which were used for the execution of previous load instructions; means responsive to said currently fetched load instruction for determining, during said decode stage of said load instruction, if the address of said one of said first plurality of registers contained in said currently fetched load instruction is stored in said physical address cache; and means for conveying to said external memory at the beginning of said execution stage of said load instruction, the previously translated physical address of said memory location corresponding to said address of said one of said first plurality of registers if said address of said one of said first plurality of registers is contained in said physical address cache.
Claim 2
Dependent Claim
353 words
In a processor of the type which processes instructions in serial stages including a fetch stage, a decode stage, an execute stage, and a write-back stage, and which includes an external memory for storing data to be executed upon, said external memory including a plurality of storage locations with each said location having a unique physical storage address, and wherein said processor further includes a first plurality of registers, each said first plurality of registers having a unique address and being arranged for storing an untranslated address corresponding to one of said external memory locations, and a second plurality of registers, each said second plurality of registers having a unique address and being arranged for storing data to be executed upon by said processor, and wherein the addresses stored in said first plurality of registers require translation to said physical external memory location addresses to permit said external memory locations to be accessed, a new and improved system for efficiently accessing the data stored in one of said external memory locations and providing said data to one of said second plurality of registers responsive to a currently fetched load instruction including the address of one of said first plurality of registers, said system comprising: a physical address cache for storing a plurality of entries including the addresses of said first plurality of registers and the corresponding translated external memory address locations for those ones of said first plurality registers which were used for the execution of previous load instructions; means responsive to said currently fetched load instruction for determining, during said decode stage of said load instruction, if the address of said one of said first plurality of registers contained in said currently fetched load instruction is stored in said physical address cache; and means for conveying to said external memory at the beginning of said execution stage of said load instruction, the previously translated physical address of said memory location corresponding to said address of said one of said first plurality of registers if said address of said one of said first plurality of registers is contained in said physical address cache.
Claim 3
Dependent Claim
20 words
A system as defined in claim 1 further including update means for updating said entries of said physical address cache.
Claim 4
Dependent Claim
43 words
A system as defined in claim 2 wherein said update means is arranged to update said physical address cache when an address of one of said first plurality of registers contained in a load instruction is not located in said physical address cache.
Claim 5
Dependent Claim
56 words
A system as defined in claim 2 wherein said update means comprises an address generator coupled to said physical address cache for generating a new translated physical address associated with a corresponding one of said first plurality of registers pursuant to the execution of an address computation instruction prior to an immediately succeeding respective load instruction.
Claim 6
Dependent Claim
40 words
A system as defined in claim 4 wherein said address generator is coupled to said external memory for conveying to said external memory said new translated physical address prior to the execution stage of said immediately succeeding respective load instruction.
Claim 7
Dependent Claim
38 words
A system as defined in claim 5 wherein said address generator is arranged to convey said new translated physical address to said physical address cache with the address of said corresponding one of said first plurality of registers.
Claim 8
Dependent Claim
36 words
A system as defined in claim 4 wherein said address generator is arranged to compute a new physical address by arithmetically processing a base address and an offset address to derive a multiple-bit new virtual address.
Claim 9
Dependent Claim
111 words
A system as defined in claim 7 wherein said address generator includes a plurality of tables, each said table containing a plurality of external memory physical addresses, computing means for generating said multiple-bit virtual address, said computing means being arranged to provide said tables a first given number of said generated bits to derive from each said table one potential physical address while said computing means generates the other of said multiple bits, and translation means coupled to said computing means and to said tables for comparing said generated multiple-bit address to said potential physical addresses to determine which one of said potential physical addresses is said new translated physical address.
Claim 10
Dependent Claim
28 words
A system as defined in claim 8 wherein said translation means is coupled to said external memory for providing said external memory with said new translated physical address.
Claim 11
Dependent Claim
31 words
A system as defined in claim 9 wherein said translation means is further coupled to said physical address cache for providing said physical address cache with said new translated physical address.
Claim 12
Dependent Claim
31 words
A system as defined in claim 10 further including select means and wherein said physical address cache and said translation means are coupled to said external memory through said select means.
Claim 13
Dependent Claim
14 words
A system as defined in claim 8 wherein said computing means comprises an adder.
Claim 14
Dependent Claim
166 words
In a processor, an address generator, for generating a multiple-bit translated external memory physical address, responsive to a base address and an offset address, said address generator comprising: a plurality of tables, each said table containing a plurality of external memory physical addresses; computing means for arithmetically processing said base address and said offset address to generate a multiple-bit virtual address, said computing means being arranged to generate said multiple-bit virtual address and to provide said tables with a given number of first generated bits; said tables being responsive to said given number of first generated bits to derive from each said table one potential translated physical address while said computing means generates the other bits of said multiple-bit virtual address; and translation means coupled to said computing means and to each of said tables for comparing said generated multiple-bit virtual address to said potential translated physical addresses to determine which one of said potential translated physical addresses is said multiple-bit translated external memory physical address.
Claim 15
Dependent Claim
166 words
In a processor, an address generator, for generating a multiple-bit translated external memory physical address, responsive to a base address and an offset address, said address generator comprising: a plurality of tables, each said table containing a plurality of external memory physical addresses; computing means for arithmetically processing said base address and said offset address to generate a multiple-bit virtual address, said computing means being arranged to generate said multiple-bit virtual address and to provide said tables with a given number of first generated bits; said tables being responsive to said given number of first generated bits to derive from each said table one potential translated physical address while said computing means generates the other bits of said multiple-bit virtual address; and translation means coupled to said computing means and to each of said tables for comparing said generated multiple-bit virtual address to said potential translated physical addresses to determine which one of said potential translated physical addresses is said multiple-bit translated external memory physical address.
Claim 16
Dependent Claim
16 words
An address generator as defined in claim 13 wherein said plurality of tables comprises two tables.
Claim 17
Dependent Claim
15 words
An address generator as defined in claim 13 wherein said computing means comprises an adder.
Claim 18
Dependent Claim
29 words
An address generator as defined in claim 15 wherein said adder comprises a first input for receiving said base address and a second input for receiving said offset address.
Claim 19
Dependent Claim
19 words
An address generator as defined in claim 13 wherein said given number of first generated bits is five bits.
Claim 20
Dependent Claim
53 words
An address generator as defined in claim 13 wherein said computing means comprises a first output coupled to said tables for providing said tables said given number of first generated bits, and a second output coupled to said translation means for providing said translation means said other bits of said multiple-bit virtual address.
Claim 21
Dependent Claim
42 words
An address generator as defined in claim 18 wherein said translation means is arranged to use said other bits of said multiple-bit virtual address to determine which one of said potential translated physical addresses is said multiple-bit translated external memory physical address.
Claim 22
Dependent Claim
19 words
An address generator as defined in claim 19 wherein said multiple-bit translated external memory physical address comprises thirty-two bits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-10 | 1996-11-09 | 1997-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-10 | 2000-11-09 | 2001-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-10 | 2004-11-09 | 2005-05-11 | $7700.00 | Window Closed / Lapsed |