US5210838A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for predicting the effective addresses of future memory load operations in a microprocessor
Assignee: Sun Microsystems Inc
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Filing: 1990-05-15
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Granted: 1993-05-11
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Expires: 2010-05-15
Abstract
Abstract A method and apparatus for loading a data value for a future LOAD instruction in a microprocessor by predicting the LOAD instruction's effective address. At each occurrence of a LOAD instruction, the effective address used is stored in a memory array which stores a last effective address and a next-to-last effective address. At a specified period before each LOAD instruction, the microprocessor loads a data value from a predicted effective memory address computed from the memory array. The predicted effective memory address is equal to the last effective address plus the difference between the last effective address and the next-to-last effective address. If the predicted effective address equals the actual effective address of the future LOAD instruction, the loaded data value is used.
Inventors
- 👤 Eric H. Jensen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 17:18
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30043; G06F9/34; G06F9/345; G06F9/3455; G06F9/38; G06F9/3824; G06F9/383; G06F9/3832
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
303 words
A method for loading a data value from a memory into a microprocessor for a future LOAD instruction, said microprocessor having a program counter containing an address of a current instruction and having a memory array comprising a plurality of memory lines, each of said memory lines comprising a last effective address field storing a last effective address and a next-to-last effective address field storing a next-to-last effective address, said method comprising the steps of: a) updating said memory array during execution of a current LOAD instruction by said microprocessor, said updating step comprising the substeps of: i) indexing into said memory array to select a first one of said memory lines using a set of low order bits from a memory address of a first instruction located before said current LOAD instruction, ii) moving the last effective address in the last effective address field of said first memory line to the next-to-last effective address field of said first memory line, and iii) storing a current effective address of the current LOAD instruction in the last effective address field of said first memory line; b) loading a data value from said memory for a future LOAD instruction, said loading step comprising the substeps of: i) indexing into said memory array to select a second one of said memory lines using a set of low order bits from said program counter, ii) predicting an effective address by adding the last effective address of said second memory line to a difference between the last effective address of said second memory line and the next-to-last effective address of said second memory line, and iii) loading said data value from said memory using said predicted effective address; and c) using said data value if the predicted effective address matches an effective address of the future LOAD instruction.
Claim 2
Independent Claim
303 words
A method for loading a data value from a memory into a microprocessor for a future LOAD instruction, said microprocessor having a program counter containing an address of a current instruction and having a memory array comprising a plurality of memory lines, each of said memory lines comprising a last effective address field storing a last effective address and a next-to-last effective address field storing a next-to-last effective address, said method comprising the steps of: a) updating said memory array during execution of a current LOAD instruction by said microprocessor, said updating step comprising the substeps of: i) indexing into said memory array to select a first one of said memory lines using a set of low order bits from a memory address of a first instruction located before said current LOAD instruction, ii) moving the last effective address in the last effective address field of said first memory line to the next-to-last effective address field of said first memory line, and iii) storing a current effective address of the current LOAD instruction in the last effective address field of said first memory line; b) loading a data value from said memory for a future LOAD instruction, said loading step comprising the substeps of: i) indexing into said memory array to select a second one of said memory lines using a set of low order bits from said program counter, ii) predicting an effective address by adding the last effective address of said second memory line to a difference between the last effective address of said second memory line and the next-to-last effective address of said second memory line, and iii) loading said data value from said memory using said predicted effective address; and c) using said data value if the predicted effective address matches an effective address of the future LOAD instruction.
Claim 3
Dependent Claim
168 words
The method as claimed in claim 1 wherein said memory array further comprises a tag field and a status bit field in each memory line of said memory array, said tag field storing a tag comprising a set of high order address bits, said status bit field storing a status bit, and said updating step (a) further comprises the substeps of: updating the status bit of said first memory line during execution of the current LOAD instruction by said microprocessor by setting the status bit of said first memory line if a set of high order bits of said memory address of said first instruction match the tag of said first memory line; and moving the set of high order bits of said memory address of said first instruction to the tag field of said first memory line during execution of the current LOAD instruction; and further wherein said loading step (b) loads said data value only if the status bit of said second memory line is set.
Claim 4
Dependent Claim
20 words
The method as claimed in claim 2 wherein said first instruction is located four instructions before said current LOAD instruction.
Claim 5
Independent Claim
314 words
An apparatus in a microprocessor for loading a data value from a memory into the microprocessor for a future LOAD instruction, said microprocessor having a program counter containing an address of a current instruction, said apparatus comprising: a) a memory array comprising a plurality of memory lines, each of said memory lines comprising a last effective address field storing a last effective address and a next-to-last effective address field storing a next-to-last effective address; b) means for updating said memory array during execution of a current LOAD instruction by said microprocessor, said updating means comprising: i) means for indexing into said memory array to select a first one of said memory lines using a set of low order bits from a memory address of a first instruction located before said current LOAD instruction, ii) means for moving the last effective address in the last effective address field of said first memory line to the next-to-last effective address field of said first memory line, and iii) means for storing a current effective address of the current LOAD instruction in the last effective address field of said first memory line; c) means for loading a data value from said memory for a future LOAD instruction, said loading means comprising: i) means for indexing into said memory array to select a second one of said memory lines using a set of low order bits from said program counter, ii) means for predicting an effective address by adding the last effective address of said second memory line to a difference between the last effective address of said second memory line and the next-to-last effective address of said second memory line, and iii) means for loading said data value from said memory using said predicted effective address; and d) means for using said data value if the predicted effective address matches an effective address of the future LOAD instruction.
Claim 6
Independent Claim
314 words
An apparatus in a microprocessor for loading a data value from a memory into the microprocessor for a future LOAD instruction, said microprocessor having a program counter containing an address of a current instruction, said apparatus comprising: a) a memory array comprising a plurality of memory lines, each of said memory lines comprising a last effective address field storing a last effective address and a next-to-last effective address field storing a next-to-last effective address; b) means for updating said memory array during execution of a current LOAD instruction by said microprocessor, said updating means comprising: i) means for indexing into said memory array to select a first one of said memory lines using a set of low order bits from a memory address of a first instruction located before said current LOAD instruction, ii) means for moving the last effective address in the last effective address field of said first memory line to the next-to-last effective address field of said first memory line, and iii) means for storing a current effective address of the current LOAD instruction in the last effective address field of said first memory line; c) means for loading a data value from said memory for a future LOAD instruction, said loading means comprising: i) means for indexing into said memory array to select a second one of said memory lines using a set of low order bits from said program counter, ii) means for predicting an effective address by adding the last effective address of said second memory line to a difference between the last effective address of said second memory line and the next-to-last effective address of said second memory line, and iii) means for loading said data value from said memory using said predicted effective address; and d) means for using said data value if the predicted effective address matches an effective address of the future LOAD instruction.
Claim 7
Dependent Claim
167 words
The apparatus as claimed in claim 4 further comprising: a tag field in each memory line of said memory array, said tag field storing a tag comprising a set of high order address bits; means for updating the tag field of said first memory line during execution of the current LOAD instruction by said microprocessor by storing a set of high order bits of said memory address of said first instruction; a status bit in each memory line of said memory array, said status bit field storing a status bit; and means for updating the status bit of said first memory line during execution of the current LOAD instruction by said microprocessor by setting the status bit of said first memory line if a set of high order bits of said memory address of said first instruction match the tag of said first memory line; wherein said data value loading means loads said data value only if the status bit of said second memory line is set.
Claim 8
Dependent Claim
20 words
The apparatus as claimed in claim 5 wherein said first instruction is located four instructions before said current LOAD instruction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-10 | 1996-11-09 | 1997-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-10 | 2000-11-09 | 2001-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-10 | 2004-11-09 | 2005-05-11 | $7700.00 | Window Closed / Lapsed |