US5210760A — Optimized pointer control system

Claim 1

Independent Claim 269 words

Pointer control logic apparatus including registers for holding pointer parameters, said logic apparatus for generating erasure signals for use in error correcting code (ECC) circuits comprising: microprocessor means connected to all other means in said pointer control logic apparatus for supervising said pointer control logic; mode selection means for signalling entry into a read-while-write mode wherein data just written to a storage medium is read to ascertain that it was written successfully; comparison means connected to said mode selection means for comparing the location value (PLOC) in already loaded pointer registers to the location value (LOCVAL) of data currently in process in said ECC circuits; signal generation means for supplying pointer signals when data for said LOCVAL is in error; first processing means connected to said comparison means and to said signal generation means for designating a pointer register for said LOCVAL in the case where no already loaded pointer register was found to correspond to said LOCVAL by said comparison means, said first processing means also including means for loading an initializing count (CNTW) into a "pointer off" circuit (POFF) located in the LOCVAL pointer register, said initializing count being a programmable value under the control of said microprocessor means; second processing means connected to said LOCVAL register for decrementing the count in said POFF circuit each time said location value contains an error free data byte until said count equals zero, in which case said LOCVAL pointer register is dropped; and third processing means for resetting said count in said POFF circuit to its initial value, CNTW, whenever said location value contains a data byte in error.

Claim 2

Dependent Claim 269 words

Pointer control logic apparatus including registers for holding pointer parameters, said logic apparatus for generating erasure signals for use in error correcting code (ECC) circuits comprising: microprocessor means connected to all other means in said pointer control logic apparatus for supervising said pointer control logic; mode selection means for signalling entry into a read-while-write mode wherein data just written to a storage medium is read to ascertain that it was written successfully; comparison means connected to said mode selection means for comparing the location value (PLOC) in already loaded pointer registers to the location value (LOCVAL) of data currently in process in said ECC circuits; signal generation means for supplying pointer signals when data for said LOCVAL is in error; first processing means connected to said comparison means and to said signal generation means for designating a pointer register for said LOCVAL in the case where no already loaded pointer register was found to correspond to said LOCVAL by said comparison means, said first processing means also including means for loading an initializing count (CNTW) into a "pointer off" circuit (POFF) located in the LOCVAL pointer register, said initializing count being a programmable value under the control of said microprocessor means; second processing means connected to said LOCVAL register for decrementing the count in said POFF circuit each time said location value contains an error free data byte until said count equals zero, in which case said LOCVAL pointer register is dropped; and third processing means for resetting said count in said POFF circuit to its initial value, CNTW, whenever said location value contains a data byte in error.

Claim 3

Dependent Claim 242 words

The pointer control logic of claim 1 further including: said mode selection means for signalling entry into a read-only mode wherein previously stored data is read; said comparison means connected to said mode selection means for comparing the location value (PLOC) in already loaded pointer registers to the location value (LOCVAL) of data currently in process in said ECC circuits; signal generation means for supplying pointer signals when data for said LOCVAL is in error; fourth processing means connected to said comparison means and to said signal generation means, for designating a pointer register for said LOCVAL in the case where no already loaded pointer register was found to correspond to said LOCVAL by said comparison means, said fourth processing means also including means for loading an initializing count, CNTR, into a pointer off circuit (POFF) located in the LOCVAL pointer register, said initalizing count being a programmable value under the control of said microprocessor means; fifth processing means connected to said register for decrementing the count in said POFF circuit each time said LOCVAL contains an error free data byte, until said count equals zero in which case said LOCVAL pointer register is dropped; and wherein said microprocessor means programs said CNTR value used for said read-only mode to a lower value than said CNTW value used in said read-while-write mode so that pointers are maintained for a greater number of error free bytes during read-while-write mode than for read-only mode.

Claim 4

Dependent Claim 241 words

Pointer control logic apparatus including registers for holding pointer parameters for generating erasure signals for use in error correcting code (ECC) circuits comprising: microprocessor means connected to all other means in said pointer control logic apparatus for supervising said pointer control logic; mode selection means for signalling entry into a read-only mode wherein previously stored data is read; comparison means connected to said mode selection means for comparing the location value (PLOC) in already loaded pointer registers to the location value (LOCVAL) of data currently in process in said ECC circuits; signal generation means for supplying pointer signals when data for said LOCVAL is in error; first processing means connected to said comparison means and to said signal generation means for designating a pointer register for said LOCVAL in the case where no already loaded pointer register was found by said comparison means, said first processing means including means for loading an initial count (CNTR) into a "pointer off" (POFF) circuit located in the LOCVAL register, said initial count being a programmable value under the control of said microprocessor means; second processing means for decrementing the count in said POFF circuit each time said LOCVAL contains an error free data byte, until said count equals zero, in which case said LOCVAL pointer register is dropped; and third processing means for resetting said count in said POFF circuit to its initial value, CNTR, whenever said LOCVAL contains a data byte in error.

Claim 5

Dependent Claim 241 words

Pointer control logic apparatus including registers for holding pointer parameters for generating erasure signals for use in error correcting code (ECC) circuits comprising: microprocessor means connected to all other means in said pointer control logic apparatus for supervising said pointer control logic; mode selection means for signalling entry into a read-only mode wherein previously stored data is read; comparison means connected to said mode selection means for comparing the location value (PLOC) in already loaded pointer registers to the location value (LOCVAL) of data currently in process in said ECC circuits; signal generation means for supplying pointer signals when data for said LOCVAL is in error; first processing means connected to said comparison means and to said signal generation means for designating a pointer register for said LOCVAL in the case where no already loaded pointer register was found by said comparison means, said first processing means including means for loading an initial count (CNTR) into a "pointer off" (POFF) circuit located in the LOCVAL register, said initial count being a programmable value under the control of said microprocessor means; second processing means for decrementing the count in said POFF circuit each time said LOCVAL contains an error free data byte, until said count equals zero, in which case said LOCVAL pointer register is dropped; and third processing means for resetting said count in said POFF circuit to its initial value, CNTR, whenever said LOCVAL contains a data byte in error.

Claim 6

Dependent Claim 152 words

The pointer control logic of claim 3 further including: means connected to said POFF circuit for setting a first pointer dropping threshold value at a POFF count between CNTR and zero, said first threshold value being a programmable value under the control of said microprocessor means; fourth processing means connected to said POFF circuit, including comparator means for determining the lowest POFF count among the already loaded (active) pointer registers, and further comparator means for determining whether said lowest POFF count is below said first threshold value, said fourth processing means further including means for replacing the contents of the active pointer register with the lowest POFF count with new contents for the LOCVAL when said lowest POFF count is below said first threshold value and when the maximum number of active pointer registers are loaded and a LOCVAL not pointed to by an active register contains a data byte in error.

Claim 7

Dependent Claim 143 words

The pointer control logic of claim 4 further including: means connected to said POFF circuit for setting a second pointer dropping threshold value at a POFF count between said CNTR and said first threshold value, said second threshold value being a programmable value under the control of said microprocessor means; said fourth processing means further including comparator means for determining whether said lowest POFF count is below said second threshold value, said fourth processing means further including means for replacing the contents of the active pointer register with the lowest POFF count with new contents for the LOCVAL, when said lowest POFF count is below said second threshold value but not below said first threshold value and when the maximum number of active pointer registers are loaded and a LOCVAL not pointed to by an active register contains a data byte in error.

Claim 8

Dependent Claim 41 words

The pointer control logic of claim 5 wherein said fourth processing means further includes: flag means for associating said second threshold value with pointers that are derived from a first class of data byte pointers that can point to potential errors.

Claim 9

Dependent Claim 235 words

The pointer control logic of claim 4 further including: n register means connected to all of said processing means and comparator means for holding pointer parameters including the POFF count and all other values and flags associated with the pointer, one register for each pointer, n equal to the maximum number of pointers for which said ECC circuits can correct errors; a first register means among said n register means, connected to said processing circuits for holding the pointer parameters, if any, corresponding to the location value (LOCVAL) of data currently in process in said ECC circuits; means connected to said n register means for shifting the contents of all active registers to shift the contents of said first register means to another register means upon processing said LOCVAL when more than one pointer register is active; means for loading said first register means upon a shift operation with pointer parameters from a second register means so that said first register means contains parameters for the next location value with an active pointer no matter how many of n pointer registers are loaded; and means for incrementing/decrementing operations for all pointer parameters when they are in said first register means; whereby the number of active registers expands and contracts with the number of active pointers to provide a variable circle of registers in which the contents are shifted one to another upon each shift operation.

Claim 10

Dependent Claim 117 words

The pointer control logic of claim 7 wherein the register whose contents are to be replaced is designated n-a where "a" can take a value from 0 to n-1, and wherein said means for replacing further includes: means for deleting the contents of register n-a; means for activating said means for shifting to move the contents of all registers with a designation greater than n-a into the next lower designated register, thereby deleting pointer parameters from register n; and means for loading register n with pointer parameters for said LOCVAL; whereby the order of pointers in said registers is preserved and said first register means continues to contain pointer parameters, if any, to the next location value.

Claim 11

Dependent Claim 235 words

The pointer control logic of claim 5 further including: n register means connected to all of said processing means and comparator means for holding pointer parameters including the POFF count and all other values and flags associated with the pointer, one register for each pointer, n equal to the maximum number of pointers for which said ECC circuits can correct errors; a first register means among said n register means, connected to said processing circuits for holding the pointer parameters, if any, corresponding to the location value (LOCVAL) of data currently in process in said ECC circuits; means connected to said n register means for shifting the contents of all active registers to shift the contents of said first register means to another register means upon processing said LOCVAL when more than one pointer register is active; means for loading said first register means upon a shift operation with pointer parameters from a second register means so that said first register means contains parameters for the next location value with an active pointer no matter how many of n pointer registers are loaded; and means for incrementing/decrementing operations for all pointer parameters when they are in said first register means; whereby the number of active registers expands and contracts with the number of active pointers to provide a variable circle of registers in which the contents are shifted one to another upon each shift operation.

Claim 12

Dependent Claim 117 words

The pointer control logic of claim 9 wherein the register whose contents are to be replaced is designated n-a where "a" can take a value from 0 to n-1, and wherein said means for replacing further includes: means for deleting the contents of register n-a; means for activating said means for shifting to move the contents of all registers with a designation greater than n-a into the next lower designated register, thereby deleting pointer parameters from register n; and means for loading register n with pointer parameters for said LOCVAL; whereby the order of pointers in said registers is preserved and said first register means continues to contain pointer parameters, if any, to the next location value.

Claim 13

Dependent Claim 235 words

The pointer control logic of claim 1 further including: n register means connected to all of said processing means and comparator means for holding pointer parameters including the POFF count and all other values and flags associated with the pointer, one register for each pointer, n equal to the maximum number of pointers for which said ECC circuits can correct errors; a first register means among said n register means, connected to said processing circuits for holding the pointer parameters, if any, corresponding to the location value (LOCVAL) of data currently in process in said ECC circuits; means connected to said n register means for shifting the contents of all active registers to shift the contents of said first register means to another register means upon processing said LOCVAL when more than one pointer register is active; means for loading said first register means upon a shift operation with pointer parameters from a second register means so that said first register means contains parameters for the next location value with an active pointer no matter how many of n pointer registers are loaded; and means for incrementing/decrementing operations for all pointer parameters when they are in said first register means; whereby the number of active registers expands and contracts with the number of active pointers to provide a variable circle of registers in which the contents are shifted one to another upon each shift operation.

Claim 14

Dependent Claim 235 words

The pointer control logic of claim 3 further including: n register means connected to all of said processing means and comparator means for holding pointer parameters including the POFF count and all other values and flags associated with the pointer, one register for each pointer, n equal to the maximum number of pointers for which said ECC circuits can correct errors; a first register means among said n register means, connected to said processing circuits for holding the pointer parameters, if any, corresponding to the location value (LOCVAL) of data currently in process in said ECC circuits; means connected to said n register means for shifting the contents of all active registers to shift the contents of said first register means to another register means upon processing said LOCVAL when more than one pointer register is active; means for loading said first register means upon a shift operation with pointer parameters from a second register means so that said first register means contains parameters for the next location value with an active pointer no matter how many of n pointer registers are loaded; and means for incrementing/decrementing operations for all pointer parameters when they are in said first register means; whereby the number of active registers expands and contracts with the number of active pointers to provide a variable circle of registers in which the contents are shifted one to another upon each shift operation.

Claim 15

Dependent Claim 73 words

The pointer control logic of claim 4 further including: means connected to said signal generation means and to said fourth processing means for activating said pointer signals for more than one data byte for said LOCVAL when the maximum number of active pointer registers are loaded, and a LOCVAL not pointed to by an active register contains a data byte in error, and said lowest POFF count is above said first threshold value.

Claim 16

Dependent Claim 78 words

The pointer control logic of claim 5 further including: means connected to said signal generation means and to said fourth processing means for activating said pointer signals for more than one data byte for said LOCVAL when the maximum number of active pointer registers are loaded, and a LOCVAL not pointed to by an active register contains a data byte in error, and said lowest POFF count is above said first threshold value and said second threshold value.

Claim 17

Independent Claim 183 words

A method of pointer control for generating erasure signals for use in error correcting code (ECC) circuits including the steps of: signalling entry into a read-while-write mode wherein data just written to a storage medium is read to ascertain that it was written successfully; comparing the location value (PLOC) in already loaded pointer registers, if any, to the location value (LOCVAL) of data currently in process in said ECC circuits; supplying pointer signals when data for said LOCVAL is in error; designating a pointer register for said LOCVAL in the case where no already loaded pointer register was found to correspond to said LOCVAL; loading an initializing count (CNTW) into a "pointer off" circuit (POFF) located in the LOCVAL pointer register, said initializing count being a programmable value; decrementing the count in said POFF circuit each time said location value contains an error free data byte until said count equals zero, in which case said LOCVAL pointer register is dropped; and resetting said count in said POFF circuit to its initial value, CNTW, whenever said location value contains a data byte in error.

Claim 18

Independent Claim 183 words

A method of pointer control for generating erasure signals for use in error correcting code (ECC) circuits including the steps of: signalling entry into a read-while-write mode wherein data just written to a storage medium is read to ascertain that it was written successfully; comparing the location value (PLOC) in already loaded pointer registers, if any, to the location value (LOCVAL) of data currently in process in said ECC circuits; supplying pointer signals when data for said LOCVAL is in error; designating a pointer register for said LOCVAL in the case where no already loaded pointer register was found to correspond to said LOCVAL; loading an initializing count (CNTW) into a "pointer off" circuit (POFF) located in the LOCVAL pointer register, said initializing count being a programmable value; decrementing the count in said POFF circuit each time said location value contains an error free data byte until said count equals zero, in which case said LOCVAL pointer register is dropped; and resetting said count in said POFF circuit to its initial value, CNTW, whenever said location value contains a data byte in error.

Claim 19

Dependent Claim 182 words

The pointer control method of claim 15 further including the steps of: signalling entry into a read-only mode wherein previously stored data is read; comparing the location value (PLOC) in already loaded pointer registers, if any, to the location value (LOCVAL) of data currently in process in said ECC circuits; supplying pointer signals when data for said LOCVAL is in error; designating a pointer register for said LOCVAL in the case where no already loaded pointer register was found to correspond to said LOCVAL; loading an initializing count, CNTR, into a pointer off circuit (POFF) located in the LOCVAL pointer register, said initalizing count being a programmable value; decrementing the count in said POFF circuit each time said LOCVAL contains an error free data byte, until said count equals zero in which case said LOCVAL pointer register is dropped; and setting said CNTR value used for said read-only mode to a lower value than said CNTW value used in said read-while-write mode so that pointers are maintained for a greater number of error free bytes during read-while-write mode than for read-only mode.

Claim 20

Independent Claim 162 words

A method of pointer control for generating erasure signals for use in error correcting code (ECC) circuits including the steps of: signalling entry into a read-only mode wherein previously stored data is read; comparing the location value (PLOC) in already loaded pointer registers to the location value (LOCVAL) of data currently in process in said ECC circuits; supplying pointer signals when data for said LOCVAL is in error; designating a pointer register for said LOCVAL in the case where no already loaded pointer register was found; loading an initial count (CNTR) into a "pointer off" (POFF) circuit located in the LOCVAL register, said initial count being a programmable value; decrementing the count in said POFF circuit each time said LOCVAL contains an error free data byte, until said count equals zero, in which case said LOCVAL pointer register is dropped; and resetting said count in said POFF circuit to its initial value, CNTR, whenever said LOCVAL contains a data byte in error.

Claim 21

Independent Claim 162 words

A method of pointer control for generating erasure signals for use in error correcting code (ECC) circuits including the steps of: signalling entry into a read-only mode wherein previously stored data is read; comparing the location value (PLOC) in already loaded pointer registers to the location value (LOCVAL) of data currently in process in said ECC circuits; supplying pointer signals when data for said LOCVAL is in error; designating a pointer register for said LOCVAL in the case where no already loaded pointer register was found; loading an initial count (CNTR) into a "pointer off" (POFF) circuit located in the LOCVAL register, said initial count being a programmable value; decrementing the count in said POFF circuit each time said LOCVAL contains an error free data byte, until said count equals zero, in which case said LOCVAL pointer register is dropped; and resetting said count in said POFF circuit to its initial value, CNTR, whenever said LOCVAL contains a data byte in error.

Claim 22

Dependent Claim 116 words

The pointer control method of claim 17 further including the steps of: setting a first pointer dropping threshold value at a POFF count between CNTR and zero, said first threshold value being a programmable value; determining the lowest POFF count among the already loaded (active) pointer registers; determining whether said lowest POFF count is below said first threshold value; replacing the contents of the active pointer register with the lowest POFF count with new contents for the LOCVAL when said lowest POFF count is below said first threshold value and when the maximum number of active pointer registers are loaded and a LOCVAL not pointed to by an active register contains a data byte in error.

Claim 23

Dependent Claim 115 words

The pointer control method of claim 18 further including the steps of: setting a second pointer dropping threshold value at a POFF count between said CNTR and said first threshold value, said second threshold value being a programmable value; determining whether said lowest POFF count is below said second threshold value; replacing the contents of the active pointer register with the lowest POFF count with new contents for the LOCVAL, when said lowest POFF count is below said second threshold value but not below said first threshold value and when the maximum number of active pointer registers are loaded and a LOCVAL not pointed to by an active register contains a data byte in error.

Claim 24

Dependent Claim 36 words

The pointer control method of claim 19 further including the steps of: associating said second threshold value with pointers that are derived from a first class of data byte pointers that can point to potential errors.

Claim 25

Dependent Claim 193 words

The pointer control method of claim 18 further including the steps of: holding pointer parameters including the POFF count and all other values and flags associated with the pointer in n registers, one register for each pointer, n equal to the maximum number of pointers for which said ECC circuits can correct errors; holding the pointer parameters, if any, corresponding to the location value (LOCVAL) of data currently in process in said ECC circuits in a first register; shifting the contents of all active registers to shift the contents of said first register upon processing said LOCVAL when more than one pointer register is active; loading said first register upon a shift operation with pointer parameters from a second register so that said first register contains parameters for the next location value with an active pointer, no matter how many of n pointer registers are loaded; and incrementing/decrementing all pointer parameters when they are in said first register; whereby the number of active registers expands and contracts with the number of active pointers to provide a variable circle of registers in which the contents are shifted one to another upon each shift operation.

Claim 26

Dependent Claim 112 words

The pointer control method of claim 21 wherein the register whose contents are to be replaced is designated n-a where "a" can take a value from 0 to n-1, and wherein said step of replacing further includes the steps of: deleting the contents of register n-a; activating said shifting step to move the contents of all registers with a designation greater than n-a into the next lower designated register, thereby deleting pointer parameters from register n; and loading register n with pointer paramters for said LOCVAL; whereby the order of pointers in said registers is preserved and said first register continues to contain pointer parameters, if any, to the next location value.

Claim 27

Dependent Claim 196 words

The pointer control method of claim 19 further including the steps of: holding pointer parameters including the POFF count and all other values and flags associated with the pointer in n registers, one register for each pointer, n equal to the maximum number of pointers for which said ECC circuits can correct errors; holding the pointer parameters, if any, corresponding to the location value (LOCVAL) of data currently in process in said ECC circuits in a first register; shifting the contents of all active registers to shift the contents of said first register to another register upon processing said LOCVAL when more than one pointer register is active; loading said first register upon a shift operation with pointer parameters from a second register so that said first register contains parameters for the next location value with an active pointer, no matter how many of n pointer registers are loaded; and incrementing/decrementing all pointer parameters when they are in said first register; whereby the number of active registers expands and contracts with the number of active pointers to provide a variable circle of registers in which the contents are shifted one to another upon each shift operation.

Claim 28

Dependent Claim 110 words

The pointer control method of claim 23 wherein the register whose contents are to be replaced is designated n-a where "a" can take a value from 0 to n-1, and wherein said step of replacing further includes: deleting the contents of register n-a; activating said shifting step to move the contents of all registers with a designation greater than n-a into the next lower designated register, thereby deleting pointer parameters from register n; and loading register n with pointer parameters for said LOCVAL; whereby the order of pointers in said registers is preserved and said first register means continues to contain pointer parameters, if any, to the next location value.

Claim 29

Dependent Claim 197 words

The pointer control method of claim 15 further including the steps of: holding pointer parameters including the POFF count and all other values and flags associated with the pointer in n register, one register for each pointer, n equal to the maximum number of pointers for which said ECC circuits can correct errors; holding the pointer parameters, if any, corresponding to the location value (LOCVAL) of data currently in process in said ECC circuits in a first register; shifting the contents of all active registers to shift the contents of said first register means to another register upon processing said LOCVAL when more than one pointer register is active; loading said first register upon a shift operation with pointer parameters from a second register so that said first register contains parameters for the next location value with an active pointer no matter how many of n pointer registers are loaded; and incrementing/decrementing all pointer parameters when they are in said first register; whereby the number of active registers expands and contracts with the number of active pointers to provide a variable circle of registers in which the contents are shifted one to another upon each shift operation.

Claim 30

Dependent Claim 193 words

The pointer control method of claim 17 further including the steps of: holding pointer parameters including the POFF count and all other values and flags associated with the pointer in n register, one register for each pointer, n equal to the maximum number of pointers for which said ECC circuits can correct errors; holding the pointer parameters, if any, corresponding to the location value (LOCVAL) of data currently in process in said ECC circuits in a first register; shifting the contents of all active registers to shift the contents of said first register upon processing said LOCVAL when more than one pointer register is active; loading said first register upon a shift operation with pointer parameters from a second register so that said first register contains parameters for the next location value with an active pointer, no matter how many of n pointer registers are loaded; and incrementing/decrementing all pointer parameters when they are in said first register; whereby the number of active registers expands and contracts with the number of active pointers to provide a variable circle of registers in which the contents are shifted one to another upon each shift operation.

Claim 31

Dependent Claim 62 words

The pointer control method of claim 18 further including the steps of: activating said pointer signals for more than one data byte for said LOCVAL when the maximum number of active pointer registers are loaded, and a LOCVAL not pointed to by an active register contains a data byte in error, and said lowest POFF count is above said first threshold value.

Claim 32

Dependent Claim 67 words

The pointer control method of claim 19 further including the steps of: activating said pointer signals for more than one data byte for said LOCVAL when the maximum number of active pointer registers are loaded, and a LOCVAL not pointed to by an active register contains a data byte in error, and said lowest POFF count is above said first threshold value and said second threshold value.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1996-05-10	1996-11-09	1997-05-11	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2000-05-10	2000-11-09	2001-05-11	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2004-05-10	2004-11-09	2005-05-11	$7700.00	Window Closed / Lapsed

Optimized pointer control system

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