US5210538A
Expired / Lapsed
US
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Glitch detection circuit and method
Assignee: Kikusui Electronics Corp
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Filing: 1991-09-12
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Granted: 1993-05-11
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Expires: 2011-09-12
Abstract
Abstract A glitch detection circuit having an A/D converter, a state holding circuit, a discrimination circuit and a storing circuit. The A/D converter samples an input signal at a predetermined sampling interval to produce digital data during a predetermined acquisition interval which is longer or equal to the sampling interval. The state holding circuit is connected to an output terminal of the A/D converter, and holds a distribution state of the digital data in the predetermined acquisition interval. The discrimination circuit detects a maximum value and a minimum value during the acquisition interval based on the digital data held in the state holding circuit, and the storing circuit stores the maximum value and the minimum value produced from the discrimination circuit for each acquisition interval. The arrangement can obviate the need for the feedback loop that limits the operation speed in a conventional circuit, and can detect maximum values and the minimum values by using the state holding circuit and discriminating circuit arranged in cascade. The circuit can approximately double the operation speed of a conventional circuit, and hence can double the sampling frequency of the analog-to-digital converter. A glitch of a half pulse width can be detected.
Inventors
- 👤 Masahiko Kuroiwa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 22:51
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/08; H03M1/0863; H03M1/12
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
132 words
A glitch detection circuit comprising: A/D converting means for sampling an input signal at predetermined sampling intervals during a predetermined acquisition interval which is longer than or equal to the sampling interval to produce digital data; state holding means connected to output terminals of said A/D converting means for holding a superimposed state of a distribution of each value of the input signal sampled during the predetermined acquisition interval as digital data; discrimination means for detecting a maximum value and a minimum value of the input signal sampled during the acquisition interval by detecting the maximum value and the minimum value of the digital data held in said state holding means; and storing means for storing the maximum value and the minimum value detected by said discrimination means for each acquisition interval.
Claim 2
Dependent Claim
132 words
A glitch detection circuit comprising: A/D converting means for sampling an input signal at predetermined sampling intervals during a predetermined acquisition interval which is longer than or equal to the sampling interval to produce digital data; state holding means connected to output terminals of said A/D converting means for holding a superimposed state of a distribution of each value of the input signal sampled during the predetermined acquisition interval as digital data; discrimination means for detecting a maximum value and a minimum value of the input signal sampled during the acquisition interval by detecting the maximum value and the minimum value of the digital data held in said state holding means; and storing means for storing the maximum value and the minimum value detected by said discrimination means for each acquisition interval.
Claim 3
Dependent Claim
213 words
A glitch detection circuit comprising: A/D converting means for sampling an input signal at predetermined sampling intervals during a predetermined acquisition interval which is longer than or equal to the sampling interval to produce digital data; state holding means connected to output terminals of said A/D converting means for holding a distribution state of the digital data produced during the predetermined acquisition interval, said state holding means including decode means, having 2 n output lines, for decoding a logic state of n-bit digital data fed from said A/D converting means, to select one of said 2 n output lines corresponding to one of 2 n logic states of the n-bit digital data to represent the logic state of the n-bit digital data, and a plurality of binary value storing means, each of said binary value storing means being connected to one of the 2 n output lines of said decode means, for storing the logic state represented by said decode means; discrimination means for detecting a maximum value and a minimum value of the input signal sampled during the acquisition interval based on the digital data held in said state holding means; and storing means for storing the maximum value and the minimum value detected by said discrimination means for each acquisition interval.
Claim 4
Dependent Claim
213 words
A glitch detection circuit comprising: A/D converting means for sampling an input signal at predetermined sampling intervals during a predetermined acquisition interval which is longer than or equal to the sampling interval to produce digital data; state holding means connected to output terminals of said A/D converting means for holding a distribution state of the digital data produced during the predetermined acquisition interval, said state holding means including decode means, having 2 n output lines, for decoding a logic state of n-bit digital data fed from said A/D converting means, to select one of said 2 n output lines corresponding to one of 2 n logic states of the n-bit digital data to represent the logic state of the n-bit digital data, and a plurality of binary value storing means, each of said binary value storing means being connected to one of the 2 n output lines of said decode means, for storing the logic state represented by said decode means; discrimination means for detecting a maximum value and a minimum value of the input signal sampled during the acquisition interval based on the digital data held in said state holding means; and storing means for storing the maximum value and the minimum value detected by said discrimination means for each acquisition interval.
Claim 5
Dependent Claim
67 words
A glitch detection circuit as in claim 2, wherein said discrimination means comprises a first priority encoder connected to 2 n output lines of said binary value storing means for producing a maximum value of the n-bit digital data, and a second priority encoder connected to said 2 n output lines of said binary value storing means for producing a mimimum value of the n-bit digital data.
Claim 6
Dependent Claim
17 words
A glitch detection circuit as in claim 2, wherein said binary value storing means includes JK flip-flops.
Claim 7
Dependent Claim
17 words
A glitch detection circuit as in claim 2, wherein said binary value storing means includes D-type flip-flops.
Claim 8
Dependent Claim
246 words
A glitch detection method comprising the steps of: (a) converting an input signal into successive n-bit digital data by sampling the input signal at predetermined sampling intervals during a predetermined acquisition interval which is longer than or equal to the sampling interval; (b) holding a distribution state of a first set of n-bit digital data produced by said conversion of said input signal at a first sampling interval during the acquisition interval by decoding the first set of n-bit digital data into 2 n -bit data and holding the 2 n -bit data; (c) changing the distribution state by decoding a next set of n-bit digital data produced by said conversion of said input signal at a next sampling interval during the acquisition interval into 2 n -bit data, comparing the 2 n -bit data of said next set with the 2 n -bit data of said first set, and updating one or more bits of the held 2 n -bit data on the basis of the comparison; (d) repeating step (c) with a succeeding set of n-bit digital data produced by said conversion of said input signal at a succeeding sampling interval during the acquisition interval; (e) detecting, after completing steps (a)-(d), a maximum value and a minimum value of the n-bit digital data produced by said conversion during the acquisition interval; and (f) storing the maximum value and the minimum value of the n-bit digital data produced by said conversion during the acquisition interval.
Claim 9
Dependent Claim
246 words
A glitch detection method comprising the steps of: (a) converting an input signal into successive n-bit digital data by sampling the input signal at predetermined sampling intervals during a predetermined acquisition interval which is longer than or equal to the sampling interval; (b) holding a distribution state of a first set of n-bit digital data produced by said conversion of said input signal at a first sampling interval during the acquisition interval by decoding the first set of n-bit digital data into 2 n -bit data and holding the 2 n -bit data; (c) changing the distribution state by decoding a next set of n-bit digital data produced by said conversion of said input signal at a next sampling interval during the acquisition interval into 2 n -bit data, comparing the 2 n -bit data of said next set with the 2 n -bit data of said first set, and updating one or more bits of the held 2 n -bit data on the basis of the comparison; (d) repeating step (c) with a succeeding set of n-bit digital data produced by said conversion of said input signal at a succeeding sampling interval during the acquisition interval; (e) detecting, after completing steps (a)-(d), a maximum value and a minimum value of the n-bit digital data produced by said conversion during the acquisition interval; and (f) storing the maximum value and the minimum value of the n-bit digital data produced by said conversion during the acquisition interval.
Claim 10
Dependent Claim
196 words
A glitch detection circuit comprising: A/D converting means for sampling an input signal at predetermined sampling intervals during a predetermined acquisition interval which is longer than or equal to the sampling interval to produce digital data; state holding means connected to output terminals of said A/D converting means for holding a distribution state of the digital data produced during the predetermined acquisition interval, said state holding means including decode means for decoding n-bit digital data produced by said A/D converting means during said acquisition interval to select one of 2 n logic states of said digital data, a plurality of binary value storing means, each of said binary value storing means corresponding to a respective one of said 2 n logic states, and means for setting respective ones of said binary value storing means which correspond to logic states selected by said decode means; discrimination means for detecting a maximum value and a minimum value of the input signal sampled during the acquisition interval based on the digital data held in said state holding means; and storing means for storing the maximum value and the minimum value detected by said discrimination means for each acquisition interval.
Claim 11
Dependent Claim
196 words
A glitch detection circuit comprising: A/D converting means for sampling an input signal at predetermined sampling intervals during a predetermined acquisition interval which is longer than or equal to the sampling interval to produce digital data; state holding means connected to output terminals of said A/D converting means for holding a distribution state of the digital data produced during the predetermined acquisition interval, said state holding means including decode means for decoding n-bit digital data produced by said A/D converting means during said acquisition interval to select one of 2 n logic states of said digital data, a plurality of binary value storing means, each of said binary value storing means corresponding to a respective one of said 2 n logic states, and means for setting respective ones of said binary value storing means which correspond to logic states selected by said decode means; discrimination means for detecting a maximum value and a minimum value of the input signal sampled during the acquisition interval based on the digital data held in said state holding means; and storing means for storing the maximum value and the minimum value detected by said discrimination means for each acquisition interval.
Claim 12
Dependent Claim
102 words
A glitch detection circuit as in claim 7, wherein said discrimination means comprises: first priority encoder means, connected to said plurality of binary value storing means, for detecting the highest logic state indicated by the set binary value storing means, and for generating a maximum value of the n-bit digital data corresponding to said highest logic state; and second priority encoder means, connected to said plurality of binary value storing means, for detecting the lowest logic state indicated by the set binary value storing means, and for generating a minimum value of the n-bit digital data corresponding to said lowest logic state.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-10 | 1996-11-09 | 1997-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-10 | 2000-11-09 | 2001-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-10 | 2004-11-09 | 2005-05-11 | $7700.00 | Window Closed / Lapsed |