Patent US2606538A successfully refreshed from Google Patents.
Patent US5210537A successfully refreshed from Google Patents.
US5210537A
Expired / Lapsed
US
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Multi-stage A/D converter
Assignee: Analog Devices Inc
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Filing: 1992-07-02
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Granted: 1993-05-11
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Expires: 2012-07-02
Abstract
Abstract An analog-to-digital converter (ADC) having two cascaded A/D stages of the parallel type wherein the analog signal is compared with a set of threshold reference voltages. The first stage develops a set of most-significant bits and produces two analog residue signals: a normal residue corresponding to the difference between the analog input and the threshold voltage below the analog input, and a second residue corresponding to the difference between the analog input and the threshold voltage above the analog signal level. These two residue signals are amplified and directed to the second A/D stage. The sum of the residue signals equals one LSB of the first A/D stage, so that the two residues supply to the second stage information about the quantization error of the previous stage as well as the quantization step size to be used to define full-scale at the second stage. The second A/D stage includes a parallel converter for developing a set of less-significant bits representing the ratio of the normal residue signal to the sum of the two residue signals. The most-significant and less-significant sets of bits are combined to provide the final digital output. Errors due to inaccuracies in interstage gain are reduced due to the use of two residue signals for generating the less-significant bits.
Inventors
- 👤 Christopher W. Mangelsdorf
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:20
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/14; H03M1/16; H03M1/164; H03M1/165; H03M1/34; H03M1/36; H03M1/361; H03M1/362
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
158 words
A multi-stage A-to-D converter, comprising: a first A/D stage arranged to receive an analog input signal to be converted to a first digital signal; first reference signal means for said first stage arranged to produce a set of reference signal levels of different magnitudes for comparison with said analog input signal to provide for producing said first digital signal of at least one most-significant bit responsive to the value of said analog input signal; residue means forming part of said first A/D stage for developing first and second residue signals representing, respectively, the differences between said analog input signal and two of said reference levels; a second A/D stage for producing a second digital signal comprising at lest one bit of less significance than said most-significant bit corresponding to at least one of said residue signals; said second A/D stage including mean responsive to both said first and said second residue signals for developing said second digital signal.
Claim 2
Dependent Claim
158 words
A multi-stage A-to-D converter, comprising: a first A/D stage arranged to receive an analog input signal to be converted to a first digital signal; first reference signal means for said first stage arranged to produce a set of reference signal levels of different magnitudes for comparison with said analog input signal to provide for producing said first digital signal of at least one most-significant bit responsive to the value of said analog input signal; residue means forming part of said first A/D stage for developing first and second residue signals representing, respectively, the differences between said analog input signal and two of said reference levels; a second A/D stage for producing a second digital signal comprising at lest one bit of less significance than said most-significant bit corresponding to at least one of said residue signals; said second A/D stage including mean responsive to both said first and said second residue signals for developing said second digital signal.
Claim 3
Dependent Claim
16 words
A converter as claimed in claim 1, including interstage amplifying means for amplifying said residue signals.
Claim 4
Dependent Claim
73 words
A converter as claimed in claim 1, including first and second amplifiers having inputs responsive to said first and second residue signals and producing amplified outputs corresponding thereto; an impedance network responsive to the outputs of said two amplifiers for producing a set of progressively-increasing second reference signals; and comparator means having inputs connected respectively to said set of second reference signals and operable to produce outputs for developing said second digital signal.
Claim 5
Dependent Claim
35 words
A converter as claimed in claim 3, wherein said impedance network comprises a series-connected string of impedance elements; the outputs of said two amplifiers being connected at opposite ends of said string of elements respectively.
Claim 6
Dependent Claim
85 words
A converter as claimed in claim 1, wherein said first reference signal means includes a series-connected string of impedance elements; first and second amplifiers; mean for connecting one input terminal of each amplifier to respective adjacent nodes of sad string which provide signal levels above and below said analog signal; means for connecting the other input terminals of said amplifiers to said analog signal; the outputs of said amplifiers producing signals corresponding to said first and second residue signals for developing said second digital signal.
Claim 7
Dependent Claim
38 words
A converter as claimed in claim 5, including a second series-connected string of impedance elements connected between the outputs of said first and second amplifiers to serve as second reference signal means for developing said second digital signal.
Claim 8
Dependent Claim
36 words
A converter as claimed in claim 6, wherein said second A/D stage comprises a set of comparators; and means connecting one input of each comparator to a corresponding node of said second string of impedance elements.
Claim 9
Dependent Claim
20 words
A converter as claimed in claim 7, wherein the other inputs of said comparators are connected to a reference potential.
Claim 10
Independent Claim
74 words
The method of converting an analog signal to a corresponding digital signal comprising; directing the analog signal to a first A/D stage for producing at least one most-significant bit; developing first and second analog residue signals representing the differences between said analog signal and first and second reference levels; and operating a second A/d stage to produce at least one less-significant bit representing a magnitude responsive to a relationship between said analog residue signal.
Claim 11
Independent Claim
74 words
The method of converting an analog signal to a corresponding digital signal comprising; directing the analog signal to a first A/D stage for producing at least one most-significant bit; developing first and second analog residue signals representing the differences between said analog signal and first and second reference levels; and operating a second A/d stage to produce at least one less-significant bit representing a magnitude responsive to a relationship between said analog residue signal.
Claim 12
Dependent Claim
15 words
The method of claim 9, wherein said most-significant bit is produced by a flash converter.
Claim 13
Dependent Claim
15 words
The method of claim 10, wherein said less-significant bit is produced by a flash converter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-10 | 1996-11-09 | 1997-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-10 | 2000-11-09 | 2001-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-10 | 2004-11-09 | 2005-05-11 | $7700.00 | Window Closed / Lapsed |