Programmable logic device

Claim 2

A programmable logic device comprising: an AND array provided with a plurality of wordlines, a plurality of bitlines substantially crossing with said plurality of wordlines, and a plurality of non-volatile memory elements, each of said memory elements having data memorized therein and being connected to one of said wordlines and one of said bitlines at each cross point of said bitlines and said wordlines, each of said wordlines having two opposed terminals; means for reading data from said plurality of non-volatile memory elements; an OR array for carrying out a predetermined calculation on the basis of data read from said plurality of non-volatile memory elements and coupled to said bitlines; an input buffer connected to one of said terminals of said wordlines; a wordline driver connected to the other of said terminals of said wordlines; and a decoder connected to the other of said terminals of said wordlines through said wordline driver, said wordline driver and said input buffer being at opposite sides of said AND array.

Claim 3

A programmable logic device according to claim 1, wherein said input buffer includes a plurality of inverters.

Claim 4

A programmable logic device according to claim 2, wherein said input buffer includes a plurality of input terminals, and each of said input terminals in connected to one of a pair of wordlines included in said plurality of wordlines through an odd number of inverters included in said plurality of inverters and is connected to the other of said pair of wordlines through an even number of inverters included in said plurality or inverters.

Claim 5

A programmable logic device operable in logic operation mode and in a program writing operation mode, said device comprising: an AND array provided with a plurality of wordlines, a plurality of bitlines substantially crossing with said plurality of wordlines, and a plurality of non-volatile memory elements, each of said memory elements having data memorized therein and being connected to one of said wordlines and one of said bitlines at a respective cross point of said bitlines and said wordlines, and a source of a program control signal, each of said wordlines having two opposed terminals and being driven when a program control signal from said source is supplied thereto; means for reading data from said plurality of non-volatile memory elements; an OR array for carrying out a predetermined calculation on the basis of data read from said plurality of non-volatile memory elements and coupled to said bitlines; an input buffer connected to the other of said terminals of said wordlines; a wordline driver connected to the other of said terminals of said wordlines; a decoder connected to the other of said terminals of said wordlines through said wordline driver, said wordline driver and said input buffer being at opposite sides of said AND array; first switching means which are open or closed selectively between said input buffer and said plurality of wordlines in response to a program control signal from said source; second switching means which are open or closed selectively between said decoder and said plurality of wordlines in response to a program control signal from said source; and a voltage applying terminal for applying voltages to said plurality of wordlines to switch said programmable logic device between said logic operation mode and said program writing operation mode.

Claim 6

A programmable logic device operable in logic operation mode and in a program writing operation mode, said device comprising: an AND array provided with a plurality of wordlines, a plurality of bitlines substantially crossing with said plurality of wordlines, and a plurality of non-volatile memory elements, each of said memory elements having data memorized therein and being connected to one of said wordlines and one of said bitlines at a respective cross point of said bitlines and said wordlines, and a source of a program control signal, each of said wordlines having two opposed terminals and being driven when a program control signal from said source is supplied thereto; means for reading data from said plurality of non-volatile memory elements; an OR array for carrying out a predetermined calculation on the basis of data read from said plurality of non-volatile memory elements and coupled to said bitlines; an input buffer connected to the other of said terminals of said wordlines; a wordline driver connected to the other of said terminals of said wordlines; a decoder connected to the other of said terminals of said wordlines through said wordline driver, said wordline driver and said input buffer being at opposite sides of said AND array; first switching means which are open or closed selectively between said input buffer and said plurality of wordlines in response to a program control signal from said source; second switching means which are open or closed selectively between said decoder and said plurality of wordlines in response to a program control signal from said source; and a voltage applying terminal for applying voltages to said plurality of wordlines to switch said programmable logic device between said logic operation mode and said program writing operation mode.

Claim 7

A programmable logic device according to claim 4, wherein said input buffer includes a plurality of inverters.

Claim 8

A programmable logic device according to claim 5, wherein said input buffer includes a plurality of input terminals, and each of said input terminals in connected to one of a pair of wordlines included in said plurality of wordlines through an odd number of inverters included in said plurality of inverters and is connected to the other of said pair of wordlines through an even number of inverters included in said plurality or inverters.

Claim 9

A programmable logic device operable in logic operation mode and in a program writing operation mode, said device comprising: an AND array provided with a plurality of wordlines, a plurality of bitlines substantially crossing with said plurality of wordlines, and a plurality of non-volatile memory elements, each of said memory elements having data memorized therein and being connected to one of said wordlines and one of said bitlines at a respective cross point of said bitlines and said wordlines, and a source of a program control signal, each of said wordlines having two opposed terminals and being driven when a program control signal from said source is supplied thereto; means for reading data from said plurality of non-volatile memory elements; an OR array for carrying out a predetermined calculation on the basis of data read from said plurality of non-volatile memory elements and coupled to said bitlines; an input buffer connected to one of said terminals of said wordlines; a wordline driver connected to the other of said terminals of said wordlines, and said wordline driver including feedback inverters each comprising a plurality of transistors connected in an inverter arrangement functioning as a positive feedback circuit in the logic operation mode; a decoder connected to the other of said terminals of said wordlines through said wordline driver, said wordline driver and said input buffer being at opposite sides of said AND array; first switching means which are open or closed selectively between said input buffer and said plurality of wordlines in response to a program control signal from said source; second switching means which are open or closed selectively between said decoder and said plurality of wordlines in response to a program control signal from said source; and a voltage applying terminal for applying voltages to said plurality of wordlines to switch said programmable logic device between the logic operation mode and the program writing operation mode.

Claim 10

A programmable logic device operable in logic operation mode and in a program writing operation mode, said device comprising: an AND array provided with a plurality of wordlines, a plurality of bitlines substantially crossing with said plurality of wordlines, and a plurality of non-volatile memory elements, each of said memory elements having data memorized therein and being connected to one of said wordlines and one of said bitlines at a respective cross point of said bitlines and said wordlines, and a source of a program control signal, each of said wordlines having two opposed terminals and being driven when a program control signal from said source is supplied thereto; means for reading data from said plurality of non-volatile memory elements; an OR array for carrying out a predetermined calculation on the basis of data read from said plurality of non-volatile memory elements and coupled to said bitlines; an input buffer connected to one of said terminals of said wordlines; a wordline driver connected to the other of said terminals of said wordlines, and said wordline driver including feedback inverters each comprising a plurality of transistors connected in an inverter arrangement functioning as a positive feedback circuit in the logic operation mode; a decoder connected to the other of said terminals of said wordlines through said wordline driver, said wordline driver and said input buffer being at opposite sides of said AND array; first switching means which are open or closed selectively between said input buffer and said plurality of wordlines in response to a program control signal from said source; second switching means which are open or closed selectively between said decoder and said plurality of wordlines in response to a program control signal from said source; and a voltage applying terminal for applying voltages to said plurality of wordlines to switch said programmable logic device between the logic operation mode and the program writing operation mode.

Claim 11

A programmable logic device according to claim 7, wherein said input buffer includes a plurality of inverters.

Claim 12

A programmable logic device according to claim 8, wherein said input buffer includes a plurality of input terminals, and each of said input terminals in connected to one of a pair of wordlines included in said plurality of wordlines through an odd number of inverters included in said plurality of inverters and is connected to the other of said pair of wordlines through an even number of inverters included in said plurality or inverters.

Claim 13

A programmable logic device operable in logic operation mode, in a program writing operation mode and in a test operation mode, said device comprising: an AND array provided with a plurality of wordlines, a plurality of bitlines substantially crossing with said plurality of wordlines, and a plurality of non-volatile memory elements, each of said memory elements having data memorized therein and being connected to one of said wordlines and one of said bitlines at a respective cross point of said bitlines and said wordlines, and a source of a program control signal, each of said wordlines having two opposed terminals and being driven when a program control signal from said source is supplied thereto; means for reading data from said plurality of non-volatile memory elements; an OR array for carrying out a predetermined calculation on the basis of data read from said plurality of non-volatile memory elements and coupled to said bitlines; an input buffer connected to one of said terminals of said wordlines; a wordline driver connected to the other of said terminals of said wordlines; a decoder connected to the other of said terminals of said wordlines through said wordline driver, said wordline driver and said input buffer being at opposite sides of said AND array; first switching means which are open or closed selectively between said input buffer and said plurality of wordlines in response to a program control signal from said source; second switching means which are open or closed selectively between said decoder and said plurality of wordlines in response to a program control signal from said source; a voltage applying terminal for applying voltages to said plurality of wordlines to switch said programmable logic device between the logic operation mode and the program writing operation mode; a source of a test control signal; and a test control terminal to which said test control signal is applied to cause the programmable logic device to operate in the test operation mode.

Claim 14

A programmable logic device operable in logic operation mode, in a program writing operation mode and in a test operation mode, said device comprising: an AND array provided with a plurality of wordlines, a plurality of bitlines substantially crossing with said plurality of wordlines, and a plurality of non-volatile memory elements, each of said memory elements having data memorized therein and being connected to one of said wordlines and one of said bitlines at a respective cross point of said bitlines and said wordlines, and a source of a program control signal, each of said wordlines having two opposed terminals and being driven when a program control signal from said source is supplied thereto; means for reading data from said plurality of non-volatile memory elements; an OR array for carrying out a predetermined calculation on the basis of data read from said plurality of non-volatile memory elements and coupled to said bitlines; an input buffer connected to one of said terminals of said wordlines; a wordline driver connected to the other of said terminals of said wordlines; a decoder connected to the other of said terminals of said wordlines through said wordline driver, said wordline driver and said input buffer being at opposite sides of said AND array; first switching means which are open or closed selectively between said input buffer and said plurality of wordlines in response to a program control signal from said source; second switching means which are open or closed selectively between said decoder and said plurality of wordlines in response to a program control signal from said source; a voltage applying terminal for applying voltages to said plurality of wordlines to switch said programmable logic device between the logic operation mode and the program writing operation mode; a source of a test control signal; and a test control terminal to which said test control signal is applied to cause the programmable logic device to operate in the test operation mode.

Claim 15

A programmable logic device according to claim 10, wherein said wordline driver includes feedback inverters each comprising a plurality of transistors connected in an inverter arrangement function as a positive feedback circuit in the logic operation mode.