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US5208872A
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Programmable remapper with single flow architecture
Assignee: United States, NATIONAL AERONAUTICS AND SPACE ADMINISTRATION THE, Administrator of
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Filing: 1990-03-30
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Granted: 1993-05-04
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Expires: 2010-03-30
Abstract
Abstract An apparatus for image processing comprising a camera for receiving an original visual image and transforming the original visual image into an analog image, a first converter for transforming the analog image of the camera to a digital image, a processor having a single flow architecture for receiving the digital image and producing, with a single algorithm, an output image, a second converter for transforming the digital image of the processor to an analog image, and a viewer for receiving the analog image, transforming the analog image into a transformed visual image for observing the transformations applied to the original visual image. The processor comprises one or more subprocessors for the parallel reception of a digital image for producing an output matrix of the transformed visual image. More particularly, the processor comprises a plurality of subprocessors for receiving in parallel and transforming the digital image for producing a matrix of the transformed visual image, and an output interface means for receiving the respective portions of the transformed visual image from the respective subprocessor for producing an output matrix of the transformed visual image.
Inventors
- 👤 Timothy E. Fisher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:16
CPC Classifications
G; G06; G06T; G06T3/00; G06T3/18
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
319 words
The method of generating image transformations of an input image to an output image in an accumulator/display memory by use of precalculated factor look up tables and address look up tables where the address lookup tables are of the type which have both an output destination address in an accumulator/display memory and a source input address in a frame buffer, where the input image is composed of input image pixels and the output image is composed of output image pixels, each output pixel being formed from a pre-image of input pixels, each pixel having a pixel value, and where the image transformations are of the type such that the sequential order in which the output image pixels are created and stored is different from the sequential order in which the input image pixels are stored, comprising the steps: (a) storing the input image pixel values in the frame buffer; (b) specifying explicitly in the address lookup tables the input pixels comprising a pre-image where the input pixels forming the pre-image may be non-contiguous and where each input pixel may be used in more than one pre-image; (c) reading the source address from the address look up table for a pre-image pixel; (d) reading the source pixel value from the image buffer for the pre-image pixel; (e) reading the factor corresponding to the pre-image pixel from the factor look up table; (f) multiplying the factor and the pixel value to form a product; (g) reading the destination address from the address look up table; (h) reading the contents of the accumulator/display memory at the destination address; (i) adding the product from step (f) to the contents read in step (h); (j) writing the sum of step (i) to the accumulator/display memory at the destination address; (k) repeating steps (c) through (j) for each remaining specified pixel in the pre-image; and (l) repeating steps (c) through (k) for each output pixel.
Claim 2
Independent Claim
319 words
The method of generating image transformations of an input image to an output image in an accumulator/display memory by use of precalculated factor look up tables and address look up tables where the address lookup tables are of the type which have both an output destination address in an accumulator/display memory and a source input address in a frame buffer, where the input image is composed of input image pixels and the output image is composed of output image pixels, each output pixel being formed from a pre-image of input pixels, each pixel having a pixel value, and where the image transformations are of the type such that the sequential order in which the output image pixels are created and stored is different from the sequential order in which the input image pixels are stored, comprising the steps: (a) storing the input image pixel values in the frame buffer; (b) specifying explicitly in the address lookup tables the input pixels comprising a pre-image where the input pixels forming the pre-image may be non-contiguous and where each input pixel may be used in more than one pre-image; (c) reading the source address from the address look up table for a pre-image pixel; (d) reading the source pixel value from the image buffer for the pre-image pixel; (e) reading the factor corresponding to the pre-image pixel from the factor look up table; (f) multiplying the factor and the pixel value to form a product; (g) reading the destination address from the address look up table; (h) reading the contents of the accumulator/display memory at the destination address; (i) adding the product from step (f) to the contents read in step (h); (j) writing the sum of step (i) to the accumulator/display memory at the destination address; (k) repeating steps (c) through (j) for each remaining specified pixel in the pre-image; and (l) repeating steps (c) through (k) for each output pixel.
Claim 3
Dependent Claim
25 words
The method of claim 1 where the addresses of input pixels forming the pre-image are functions of the desired transformation characteristics and may be non-contiguous.
Claim 4
Dependent Claim
16 words
The method of claim 1 where the pre-images may be of variable size and may overlap.
Claim 5
Independent Claim
302 words
The method of performing image transformations of an input image to an output image in an output memory by use of precalculated factor look up tables and address look up tables where the address lookup tables are of the type which addresses only pixels in a frame buffer, where the input image is composed of input image pixels and the output image is composed of output image pixels, each output pixel being formed from a pre-image of input pixels, each pixel having a pixel value, and where the image transformations are of the type such that the sequential order in which the output image pixels are created and stored is different from the sequential order in which the input image pixels are stored, comprising the steps: (a) storing the input image pixel values in the frame buffer; (b) creating the output pixels in a prescribed order, as follows: (1) specifying explicitly in the address look up table the number and addresses of input pixels for the pre-image where the number and addresses of input pixels are functions of the transform being performed, input pixels may be non-contiguous, and each input pixel may be used in more than one pre-image; (2) reading the source address from the address look up table for a pre-image pixel; (3) reading the source pixel value from the image buffer for the pre-image pixel; (4) reading the factor corresponding to the pre-image pixel from the factor look up table; (5) multiplying the factor and the pixel value; (6) accumulating the product from step (5) with any previous values for that pre-image in an accumulator register; (7) repeating steps (2) through (6) until pre-image is complete; (8) writing the contents of the accumulator register to an output memory; (c) repeating steps (1) through (8) until image transformation is complete.
Claim 6
Independent Claim
302 words
The method of performing image transformations of an input image to an output image in an output memory by use of precalculated factor look up tables and address look up tables where the address lookup tables are of the type which addresses only pixels in a frame buffer, where the input image is composed of input image pixels and the output image is composed of output image pixels, each output pixel being formed from a pre-image of input pixels, each pixel having a pixel value, and where the image transformations are of the type such that the sequential order in which the output image pixels are created and stored is different from the sequential order in which the input image pixels are stored, comprising the steps: (a) storing the input image pixel values in the frame buffer; (b) creating the output pixels in a prescribed order, as follows: (1) specifying explicitly in the address look up table the number and addresses of input pixels for the pre-image where the number and addresses of input pixels are functions of the transform being performed, input pixels may be non-contiguous, and each input pixel may be used in more than one pre-image; (2) reading the source address from the address look up table for a pre-image pixel; (3) reading the source pixel value from the image buffer for the pre-image pixel; (4) reading the factor corresponding to the pre-image pixel from the factor look up table; (5) multiplying the factor and the pixel value; (6) accumulating the product from step (5) with any previous values for that pre-image in an accumulator register; (7) repeating steps (2) through (6) until pre-image is complete; (8) writing the contents of the accumulator register to an output memory; (c) repeating steps (1) through (8) until image transformation is complete.
Claim 7
Dependent Claim
49 words
The method of claim 4 where the order, step (b), in which the output pixels are created is the sequential order of their output locations, and comprising the further step; (9) incrementing the output memory address; and where step (c) is the step of repeating steps (1) through (9).
Claim 8
Dependent Claim
21 words
The method of claim 4 where any input pixel may be used in the pre-image of more than one output pixel.
Claim 9
Dependent Claim
221 words
A processing system for receiving a set of input pixels and transforming them into a corresponding set of output pixels, each input pixel having a pixel value, comprising; (a) means for receiving a set of input pixels; (b) processor means for performing a first transformation of a first subset of said set of input pixels into a first subset of output pixels, and a second transformation of a second subset of said set of input pixels into a second subset of output pixels and in which the second subset of input pixels may be different from the first subset and the second transformation may be different from the first transformation, wherein, the processor means further comprises; (1) frame buffer means for storing, in a first sequential order, input pixels; (2) output memory means for storing output pixels; (3) addressing means for addressing pixel values stored in the frame buffer; the number of pixels addressed, the explicit accumulation to form an output pixel which is sent to the output memory means, the adder means and the temporary storage means thus forming a feedback loop; (10) sequencing logic means for providing the address in the output memory to which the output pixel is sent and for causing the output pixel accumulated in the feedback loop to be written to the output memory means.
Claim 10
Dependent Claim
221 words
A processing system for receiving a set of input pixels and transforming them into a corresponding set of output pixels, each input pixel having a pixel value, comprising; (a) means for receiving a set of input pixels; (b) processor means for performing a first transformation of a first subset of said set of input pixels into a first subset of output pixels, and a second transformation of a second subset of said set of input pixels into a second subset of output pixels and in which the second subset of input pixels may be different from the first subset and the second transformation may be different from the first transformation, wherein, the processor means further comprises; (1) frame buffer means for storing, in a first sequential order, input pixels; (2) output memory means for storing output pixels; (3) addressing means for addressing pixel values stored in the frame buffer; the number of pixels addressed, the explicit accumulation to form an output pixel which is sent to the output memory means, the adder means and the temporary storage means thus forming a feedback loop; (10) sequencing logic means for providing the address in the output memory to which the output pixel is sent and for causing the output pixel accumulated in the feedback loop to be written to the output memory means.
Claim 11
Dependent Claim
16 words
The processing system of claim 7, wherein, the sequencing logic means increments the output memory address.
Claim 12
Dependent Claim
30 words
The processing system of claim 7, wherein, the sequencing logic means includes a counter means and a decoder means for loading counter means to address any desired output memory location.
Claim 13
Dependent Claim
57 words
The processing system of claim 7, wherein, the frame buffer means and the output memory means are adapted to perform the reading of input pixels on a frame by frame basis and writing of output pixels on a frame by frame basis, and where the reading of input frames and writing of output frames are performed asynchronously.
Claim 14
Independent Claim
97 words
The method of processing a set of input pixels into a set of output pixels, where each output pixel is created from a subset of input pixels, comprising the steps; (a) forming one or more subsets of input pixels; wherein the input pixels may be of variable number up to the total number of input pixels, the input pixels may be noncontiguous, and wherein each subset may contain any input pixel and each subset of input pixels may be formed independently of any other subset, and (b) transforming each subset of input pixels into an output pixel.
Claim 15
Independent Claim
97 words
The method of processing a set of input pixels into a set of output pixels, where each output pixel is created from a subset of input pixels, comprising the steps; (a) forming one or more subsets of input pixels; wherein the input pixels may be of variable number up to the total number of input pixels, the input pixels may be noncontiguous, and wherein each subset may contain any input pixel and each subset of input pixels may be formed independently of any other subset, and (b) transforming each subset of input pixels into an output pixel.
Claim 16
Dependent Claim
75 words
The method of claim 11 where the input and output pixels may be represented as functions of input and output coordinates and where the relationship between the input coordinates and the output coordinates may be represented by a Jacobian matrix, further comprising the steps; (c) performing an interpolative transformation when the determinant of the Jacobian is greater than unity; and (d) performing a collective transformation when the determinant of the Jacobian is less than unity.
Claim 17
Dependent Claim
61 words
The method of claim 11 wherein the single processor means operates in accordance with the equation; ##EQU7## where; O(u,v) is the output pixel being created; {i,j} are indices defining the subset of input pixels and are functions of u,v; I(x i ,y j ) are the addresses of source pixels in the subset of input pixels; and w(i,j;u,v) are weighting factors.
Claim 18
Dependent Claim
151 words
The method of claim 11 wherein the process of transforming the first subset of input pixels and the second subset of input pixels comprises the following steps; (a) storing, in a first sequential order, the set of input pixels; (b) storing in factor lookup tables, precalculated weighting factors for each input pixel; (c) addressing, in a second sequential order, by means of address lookup tables, the stored pixels comprising the subset of input pixels; (d) reading each of the addressed pixel values; (e) reading the corresponding weighting factor for each addressed pixel; (f) multiplying each addressed pixel value and its corresponding weighting factor to produce a product; (g) repeating steps (d) through (f) and accumulating the products for all the pixels in the subset for an output pixel; (h) storing the accumulated product as the output pixel; and (i) repeating steps (c) through (h) until set of output pixels is complete.
Claim 19
Dependent Claim
29 words
The method of claim 14 where the addresses of input pixels forming the subset are functions of the desired transformation and the subset of input pixels may be non-contiguous.
Claim 20
Dependent Claim
19 words
The method of claim 14, wherein, the reading of input pixels and storing of output pixels are performed asynchronously.
Claim 21
Dependent Claim
18 words
The method of claim 14 where the first sequential order is the same as the second sequential order.
Claim 22
Dependent Claim
19 words
The method of claim 14 where the first sequential order is not the same as the second sequential order.
Claim 23
Independent Claim
100 words
The method of processing a set of input pixels into a set of output pixels, where each output pixel is formed from a subset of input pixels, said subset of input pixels being of variable number up to the total number of input pixels, comprising the steps; (a) specifying explicitly the address of each input pixel in the subset of input pixels, where the input pixels of any subset may be non-contiguous, and where any input pixel may be used in more than one subset of input pixels, and (b) transforming each subset of input pixels into an output pixel.
Claim 24
Independent Claim
100 words
The method of processing a set of input pixels into a set of output pixels, where each output pixel is formed from a subset of input pixels, said subset of input pixels being of variable number up to the total number of input pixels, comprising the steps; (a) specifying explicitly the address of each input pixel in the subset of input pixels, where the input pixels of any subset may be non-contiguous, and where any input pixel may be used in more than one subset of input pixels, and (b) transforming each subset of input pixels into an output pixel.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-03 | 1996-11-02 | 1997-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-03 | 2000-11-02 | 2001-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-03 | 2004-11-02 | 2005-05-04 | $7700.00 | Window Closed / Lapsed |