Memory unit delay-compensating circuit

Claim 2

A memory unit comprising: an array of memory cells which has a capacity of n-words by m-bits where the characters "m" and "n" denote preset natural numbers; word lines connected to the memory cells; bit lines connected to the memory cells; a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal and having k-bits where the character "k" denotes a preset natural number which satisfies a relationship as "2 k ≧n", the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2; delaying means for delaying the clock signal by a preset time "t" and thereby converting the clock signal into a control signal; means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal; and means for precharging the bit lines at a timing determined by the control signal; wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, and wherein the delaying means includes a delay causing component substantially identical in structure to a part of the decoder causing variation in the time t2, thereby to adjust the time "t" to compensate for the variation of the time t2.

Claim 3

The memory unit of claim 1, wherein said delay causing component includes means for increasing the time "t" to compensate for increases in the time t2 and for decreasing the time "t" to compensate for decreases in the time t2.

Claim 4

The memory circuit of claim 1, wherein said delaying means comprises means for time-shifting both leading and trailing edges of said clock signal by said preset time period "t".

Claim 5

A memory unit comprising: an array of memory cells; word lines connected to the memory cells; bit lines connected to the memory cells; a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal, the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2; delaying means for delaying the clock signal by a preset time "t" and thereby converting the clock signal into a control signal; means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal; and means for precharging the bit lines at a timing determined by the control signal; wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, and wherein the delaying means includes a delay causing component substantially identical in structure to a part of the decoder causing variation in the time t2, thereby to adjust the time "t" to compensate for the variation of the time t2.

Claim 6

A memory unit comprising: an array of memory cells; word lines connected to the memory cells; bit lines connected to the memory cells; a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal, the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2; delaying means for delaying the clock signal by a preset time "t" and thereby converting the clock signal into a control signal; means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal; and means for precharging the bit lines at a timing determined by the control signal; wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, and wherein the delaying means includes a delay causing component substantially identical in structure to a part of the decoder causing variation in the time t2, thereby to adjust the time "t" to compensate for the variation of the time t2.

Claim 7

The memory unit of claim 4, wherein said delay causing component includes means for increasing the time "t" to compensate for increases in the time t2 and for decreasing the time "t" to compensate for decreases in the time t2.

Claim 8

A memory unit comprising: an array of memory cells; word lines connected to the memory cells; a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal, the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2; delaying means for delaying the clock signal by a preset time "t" and thereby converting the clock signal into a control signal; and means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal; wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, and wherein the delaying means includes a delay causing component substantially identical in structure to a part of the decoder causing variation in the time t2, thereby to adjust the time "t" to compensate for the variation of the time t2.

Claim 9

A memory unit comprising: an array of memory cells; word lines connected to the memory cells; a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal, the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2; delaying means for delaying the clock signal by a preset time "t" and thereby converting the clock signal into a control signal; and means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal; wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, and wherein the delaying means includes a delay causing component substantially identical in structure to a part of the decoder causing variation in the time t2, thereby to adjust the time "t" to compensate for the variation of the time t2.

Claim 10

A memory unit comprising: an array of memory cells which has a capacity of n-words by m-bits where the characters "m" and "n" denote preset natural numbers; word lines connected to the memory cells; bit lines connected to the memory cells; a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal and having k-bits where the character "k" denotes a preset natural number which satisfies a relationship as "2 k ≧n", the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2 exposed to variation; delaying means for delaying the clock signal by a preset time "t" and thereby converting the clock signal into a control signal; means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal; and means for precharging the bit lines at a timing determined by the control signal; wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, and wherein the delaying means comprises means for adjusting the time "t" in accordance with the variation of the time t2 thereby to compensate for the variation of the time t2.

Claim 11

A memory unit comprising: an array of memory cells which has a capacity of n-words by m-bits where the characters "m" and "n" denote preset natural numbers; word lines connected to the memory cells; bit lines connected to the memory cells; a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal and having k-bits where the character "k" denotes a preset natural number which satisfies a relationship as "2 k ≧n", the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2 exposed to variation; delaying means for delaying the clock signal by a preset time "t" and thereby converting the clock signal into a control signal; means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal; and means for precharging the bit lines at a timing determined by the control signal; wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, and wherein the delaying means comprises means for adjusting the time "t" in accordance with the variation of the time t2 thereby to compensate for the variation of the time t2.

Claim 12

The memory unit of claim 7, wherein said delay causing component includes means for increasing the time "t" to compensate for increases in the time t2 and for decreasing the time "t" compensate for decreases in the time t2.

Claim 13

The memory circuit of claim 7, wherein said delaying means comprises means for time-shifting both leading and trailing edges of said clock signal by said preset time period "t".

Claim 14

A memory unit comprising: an array of memory cells; word lines connected to the memory cells; bit lines connected to the memory cells; a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal, the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2 exposed to variation; delaying means for delaying the clock signal by a preset time "t" and thereby converting the clock signal into a control signal; means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal; and means for precharging the bit lines at a timing determined by the control signal; wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, and wherein the delaying means comprises means for the adjusting the time "t" in accordance with the variation of the time t2 thereby to compensate for the variation of the time t2.

Claim 15

A memory unit comprising: an array of memory cells; word lines connected to the memory cells; bit lines connected to the memory cells; a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal, the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2 exposed to variation; delaying means for delaying the clock signal by a preset time "t" and thereby converting the clock signal into a control signal; means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal; and means for precharging the bit lines at a timing determined by the control signal; wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, and wherein the delaying means comprises means for the adjusting the time "t" in accordance with the variation of the time t2 thereby to compensate for the variation of the time t2.

Claim 16

A memory unit comprising: an array of memory cells; work lines connected to the memory cells; a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal, the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2 exposed to an variation; delaying means for delaying the clock signal by a preset time "t" and thereby converting the clock signal into a control signal; and means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal; wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, and wherein the delaying means comprises means for adjusting the time "t" in accordance with the variation of the time t2 thereby to compensate for the variation of the time t2.

Claim 17

A memory unit comprising: an array of memory cells; work lines connected to the memory cells; a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal, the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2 exposed to an variation; delaying means for delaying the clock signal by a preset time "t" and thereby converting the clock signal into a control signal; and means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal; wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, and wherein the delaying means comprises means for adjusting the time "t" in accordance with the variation of the time t2 thereby to compensate for the variation of the time t2.

Claim 18

In a memory unit including an array of memory cells; a plurality of word lines connected to the memory cells; a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal, the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2; access means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal, and a control circuit for controlling timing of activating a selected one of said word lines, the improvement comprising: generating means for generating a control signal for activating said access means, said generating means including timing means for providing a transition in said control signal at a time different by a preset time "t" for a corresponding transition in said clock signal, wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, thereby to speed up activation of the selected work line and transfer of data.

Claim 19

In a memory unit including an array of memory cells; a plurality of word lines connected to the memory cells; a decoder receiving an address signal at a timing which follows a timing of an occurrence of a clock signal by a given time t1, the address signal being in synchronism with the clock signal, the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2; access means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal, and a control circuit for controlling timing of activating a selected one of said word lines, the improvement comprising: generating means for generating a control signal for activating said access means, said generating means including timing means for providing a transition in said control signal at a time different by a preset time "t" for a corresponding transition in said clock signal, wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, thereby to speed up activation of the selected work line and transfer of data.

Claim 20

A memory unit as recited in claim 12 wherein said timing means comprises delaying means for delaying the clock signal by said preset time "t" and thereby converting the clock signal into said control signal.

Claim 21

The memory circuit of claim 13, wherein said means for delaying comprises means for time-shifting both leading and trailing edges of said clock signal by said preset time period "t".

Claim 22

A memory unit as recited in claim 12 wherein said time t2 is subjected to variation and said timing means comprises means for adjusting the time "t" in accordance with the variation of the time t2 thereby to compensate for the variation of the time t2.

Claim 23

The memory unit of claim 15, wherein said means for adjusting includes means for increasing the time "t" to compensate for increases in the time t2 and for decreasing the time "t" to compensate for decreases in the time t2.

Claim 24

A memory unit as recited in claim 12 wherein said generating means includes means for using said clock signal to generate said control signal.

Claim 25

A memory unit as recited in claim 17 wherein said timing means comprises means for delaying the clock signal by said preset time "t" and thereby converting the clock signal into said control signal.

Claim 26

The memory unit as recited in claim 17 wherein said timing means comprises a logic circuit including interconnected flip flops and logic gates responsive to outputs thereof for delaying the clock signal by said preset time "t" and thereby converting the clock signal into said control signal.

Claim 27

A memory unit as recited in claim 12 wherein said time t1 is subjected to variation in an address circuit generating said address signal and said timing means comprises compensating means for adjusting the time "t" in accordance with the variation of the time t1 thereby to compensate for the variation of the time t1.

Claim 28

A memory unit as recited in claim 20 wherein said compensating means comprises flip-flop means corresponding to a similar flip-flop means causing said variation of said time t1 in the address circuit thereby to compensate for variations in said time t1 caused by variation in a temperature of the similar flip-flop means and by fluctuation in a voltage applied to the similar flip-flop means.

Claim 29

A memory unit as recited in claim 21 wherein said time t2 is subjected to variation in said decoder and said compensating means further comprises second means for adjusting the time "t" in accordance with the variation of the time t2 thereby to compensate for the variation of the time t2 in said decoder.

Claim 30

A memory unit as recited in claim 22 wherein said second means comprises logic means corresponding to similar logic means producing said variation of said time t2 in said decoder thereby to compensate for variations in said time t2 caused by variation in a temperature of the similar logic means and by fluctuation in a voltage applied to the similar logic means.

Claim 31

The memory unit of claim 20, wherein said compensating means includes means for increasing the time "t" to compensate for increases in the time t2 and for decreasing the time "t" to compensate for decreases in the time t2.

Claim 32

A memory unit for use in combination with an address signal output circuit which latches an original address signal in response to the clock signal, the memory unit comprising: an array of memory cells which has a capacity of n-words by m-bits where the characters "m" and "n" denote preset natural numbers; word lines connected to the memory cells; bit lines connected to the memory cells; a decoder receiving an address signal from the address signal output circuit at a timing which follows a timing of an occurrence of a clock signal by a given time t1 which is determined by a signal delay time in the address signal output circuit, the address signal being in synchronism with the clock signal and having k-bits where the character "k" denotes a preset natural number which satisfies a relationship as "2 k ≧n", the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2; delaying means for delaying the clock signal by a preset time "t" thereby converting the clock signal into a control signal; means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal; and means for precharging the bit lines at a timing determined by the control signal; wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, wherein the delaying means comprises a first delay causing circuit portion and a second delay causing circuit portion, wherein the first delay causing circuit portion of the delaying means has a substantially identical structure to a third circuit portion of the decoder for adjusting the time "t" in accordance with variation of the time t2 caused by the third circuit portion, thereby to compensate for the variation of the time t2, and wherein the second delay causing circuit portion of the delaying means has a substantially identical structure to a fourth circuit portion of the address signal output circuit for adjusting the time "t" in accordance with an variation of the time t1 caused by the fourth circuit portion, thereby to compensate for the variation of the time t1.

Claim 33

A memory unit for use in combination with an address signal output circuit which latches an original address signal in response to the clock signal, the memory unit comprising: an array of memory cells which has a capacity of n-words by m-bits where the characters "m" and "n" denote preset natural numbers; word lines connected to the memory cells; bit lines connected to the memory cells; a decoder receiving an address signal from the address signal output circuit at a timing which follows a timing of an occurrence of a clock signal by a given time t1 which is determined by a signal delay time in the address signal output circuit, the address signal being in synchronism with the clock signal and having k-bits where the character "k" denotes a preset natural number which satisfies a relationship as "2 k ≧n", the clock signal having a preset period t0, the decoder decoding the address signal into a word signal and outputting the word signal at a timing which follows a timing of the reception of the address signal by a given time t2; delaying means for delaying the clock signal by a preset time "t" thereby converting the clock signal into a control signal; means for performing an access to a word of the memory cells via one of the word lines in accordance with the word signal at a timing determined by the control signal; and means for precharging the bit lines at a timing determined by the control signal; wherein the preset time "t" is longer than a sum of the times t1 and t2 but shorter than a half of the period t0, wherein the delaying means comprises a first delay causing circuit portion and a second delay causing circuit portion, wherein the first delay causing circuit portion of the delaying means has a substantially identical structure to a third circuit portion of the decoder for adjusting the time "t" in accordance with variation of the time t2 caused by the third circuit portion, thereby to compensate for the variation of the time t2, and wherein the second delay causing circuit portion of the delaying means has a substantially identical structure to a fourth circuit portion of the address signal output circuit for adjusting the time "t" in accordance with an variation of the time t1 caused by the fourth circuit portion, thereby to compensate for the variation of the time t1.

Claim 34

The memory unit of claim 25 wherein said first delay causing circuit portion and said third circuit portion have substantially identical physical structures, and wherein said second delay causing circuit portion and said fourth circuit portion have substantially identical circuit element.

Claim 35

The memory unit of claim 25, wherein said first delay causing circuit portion includes means for increasing the time "t" to compensate for increases in the time t2 and for decreasing the time "t" to compensate for decreases in the time t2, and wherein said second delay causing circuit portion includes means for increasing the time "t" to compensate for increases in the time t1 and for decreasing the time "t" to compensate for decreases in the time t1.

Claim 36

The memory circuit of claim 25, wherein said delaying means comprises means for time-shifting both leading and trailing edges of said clock signal by said preset time period "t".