Patent US5208719A successfully refreshed from Google Patents.
US5208719A
Expired / Lapsed
US
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Output pad electrostatic discharge protection circuit for mos devices
Assignee: LSI Corp
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Filing: 1991-08-20
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Granted: 1993-05-04
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Expires: 2011-08-20
Abstract
Abstract A circuit protects the series coupled PMOS-NMOS transistor output stage, input stage or input/output stage commonly found in a CMOS device from output pad ESD, whether or not the CMOS device is mounted in a circuit board or coupled to a power source. The circuit includes a second PMOS transistor whose output leads are coupled between the output pad and the gate of the output NMOS transistor, and also includes a resistor coupled between the gate of this second PMOS transistor and a voltage source node. A positive potential ESD at the output pad will turn on the second PMOS transistor, thereby coupling positive ESD potential to the gate of the output NMOS transistor. This causes the output NMOS transistor to turn on, avoiding the "snapback" mode destruction that would occur if the second PMOS transistor were not present. The resistor cooperates with the intrinsic capacitance present at the gate of the second PMOS transistor to form an RC filter that prevents noise transients coupled to this gate from turning on the second PMOS transistor. A second preferred embodiment is a protective circuit that includes the above described series coupled output PMOS, NMOS transistors, the second PMOS transistor, and the resistor. This embodiment provides output pad ESD protection to other circuits (drivers, for example) coupled to the input gate of the output transistors, or circuits (input buffers, for example), coupled to the output pad.
Inventors
- 👤 Yi-Hen Wei
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:56
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H03; H03K; H03K19/00; H03K19/003; H03K19/00315
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
131 words
In a CMOS device that includes an output PMOS transistor coupled in series with an output NMOS transistor, the PMOS and NMOS transistors each including first and second output leads and a gate, the first output leads being coupled to an output pad, an output protection circuit comprising: a second PMOS transistor, including a gate coupled to a voltage source node in the circuit, a first output lead coupled to the output pad, and a second output lead coupled to the gate of the output NMOS transistor; whereby a positive ESD potential at said output pad turns on said second PMOS transistor, thereby turning on the output NMOS transistor; said output NMOS transistor being protected thereby from snapback mode destruction that would occur in the absence of the output protection circuit.
Claim 2
Dependent Claim
131 words
In a CMOS device that includes an output PMOS transistor coupled in series with an output NMOS transistor, the PMOS and NMOS transistors each including first and second output leads and a gate, the first output leads being coupled to an output pad, an output protection circuit comprising: a second PMOS transistor, including a gate coupled to a voltage source node in the circuit, a first output lead coupled to the output pad, and a second output lead coupled to the gate of the output NMOS transistor; whereby a positive ESD potential at said output pad turns on said second PMOS transistor, thereby turning on the output NMOS transistor; said output NMOS transistor being protected thereby from snapback mode destruction that would occur in the absence of the output protection circuit.
Claim 3
Dependent Claim
30 words
The output protection circuit of claim 1, further including a resistor coupled in series between said gate of said second PMOS transistor and said voltage source node in the circuit.
Claim 4
Dependent Claim
22 words
The output protection circuit of claim 2, wherein said second output lead of said output PMOS transistor is said voltage source node.
Claim 5
Dependent Claim
19 words
The output protection circuit of claim 2, wherein said resistor has a resistance between 200 Ω and 10,000 Ω.
Claim 6
Dependent Claim
38 words
The output protection circuit of claim 2, wherein said resistor is a resistive circuit element chosen from the group consisting of a polysilicon resistor, a polycide resistor, a P + diffusion resistor, and an N + diffusion resistor.
Claim 7
Dependent Claim
49 words
The output protection circuit of claim 2, wherein said resistor forms an RC low pass filter in conjunction with intrinsic capacitance present at said gate of said second PMOS transistor; said low pass filter preventing said second PMOS transistor from being turned on by transients coupled through said resistor.
Claim 8
Dependent Claim
30 words
The output protection circuit of claim 1, wherein said gate of the output PMOS transistor and said gate of the output NMOS transistor are coupled together to form an inverter.
Claim 9
Dependent Claim
37 words
The output protection circuit of claim 1, wherein a power source is coupled to a chosen one of the second output lead of the output PMOS transistor, and the second output lead of the output NMOS transistor.
Claim 10
Dependent Claim
185 words
In a CMOS input buffer device that includes an input lead coupled to an input pad, an input protection circuit comprising: an output PMOS transistor coupled in series with an output NMOS transistor, said PMOS and NMOS transistors each including a gate, a first output lead coupled to the input pad, and a second output lead; said gate and second output lead of said output PMOS transistor being coupled together to a first voltage source node; said gate and second output lead of said output NMOS transistor being coupled together to a second voltage source node; and a second PMOS transistor, including a gate coupled to said first voltage source node, a first output lead coupled to the input pad, and a second output lead coupled to said gate of said output NMOS device; whereby a positive ESD potential at said input pad turns on said second PMOS transistor, thereby turning on said output NMOS transistor; the input buffer device being protected thereby from damage from said positive ESD potential at said input pad that would occur int he absence of said input protection circuit.
Claim 11
Dependent Claim
185 words
In a CMOS input buffer device that includes an input lead coupled to an input pad, an input protection circuit comprising: an output PMOS transistor coupled in series with an output NMOS transistor, said PMOS and NMOS transistors each including a gate, a first output lead coupled to the input pad, and a second output lead; said gate and second output lead of said output PMOS transistor being coupled together to a first voltage source node; said gate and second output lead of said output NMOS transistor being coupled together to a second voltage source node; and a second PMOS transistor, including a gate coupled to said first voltage source node, a first output lead coupled to the input pad, and a second output lead coupled to said gate of said output NMOS device; whereby a positive ESD potential at said input pad turns on said second PMOS transistor, thereby turning on said output NMOS transistor; the input buffer device being protected thereby from damage from said positive ESD potential at said input pad that would occur int he absence of said input protection circuit.
Claim 12
Dependent Claim
28 words
The input protection circuit of claim 9, further including a resistor coupled in series between said gate of said second PMOS transistor and said first voltage source node.
Claim 13
Dependent Claim
18 words
The input protection of claim 10, wherein said resistor has a resistance between 200 Ω and 10,000 Ω.
Claim 14
Dependent Claim
38 words
The input protection circuit of claim 10, wherein said resistor is a resistive circuit element chosen from the group consisting of a polysilicon resistor, a polycide resistor, a P + diffusion resistor, and an N + diffusion resistor.
Claim 15
Dependent Claim
49 words
The input protection circuit of claim 10, wherein said resistor forms an RC low pass filter in conjunction with intrinsic capacitance present at said gate of said second PMOS transistor; said low pass filter preventing said second PMOS transistor from being turned on by transients coupled through said resistor.
Claim 16
Dependent Claim
198 words
In a CMOS output buffer device having first and second input/output drivers, each driver having an input lead and an output lead, an output protection circuit comprising: an output pad; an output PMOS transistor coupled in series with an output NMOS transistor, said PMOS and NMOS transistors each including a first output lead coupled to said output pad, said PMOS transistor further including a second output lead, and a gate, said gate coupled to the output lead of the first input/output driver; said NMOS transistor further including a second output lead and a gate, said gate coupled to the output lead of the second input/output driver; and a second PMOS transistor, including a gate coupled to a voltage source node in the circuit, a first output lead coupled to said output pad, and a second output lead coupled to said gate of said output NMOS device; whereby a positive ESD potential at said output pad turns on said second PMOS transistor, thereby turning on said output NMOS transistor; the output buffer device being protected thereby from damage from said positive ESD potential at said output pad that would occur in the absence of said output pad protection circuit.
Claim 17
Dependent Claim
198 words
In a CMOS output buffer device having first and second input/output drivers, each driver having an input lead and an output lead, an output protection circuit comprising: an output pad; an output PMOS transistor coupled in series with an output NMOS transistor, said PMOS and NMOS transistors each including a first output lead coupled to said output pad, said PMOS transistor further including a second output lead, and a gate, said gate coupled to the output lead of the first input/output driver; said NMOS transistor further including a second output lead and a gate, said gate coupled to the output lead of the second input/output driver; and a second PMOS transistor, including a gate coupled to a voltage source node in the circuit, a first output lead coupled to said output pad, and a second output lead coupled to said gate of said output NMOS device; whereby a positive ESD potential at said output pad turns on said second PMOS transistor, thereby turning on said output NMOS transistor; the output buffer device being protected thereby from damage from said positive ESD potential at said output pad that would occur in the absence of said output pad protection circuit.
Claim 18
Dependent Claim
27 words
The output protection circuit of claim 14, further including a resistor coupled in series between said gate of said second PMOS transistor and said voltage source node.
Claim 19
Dependent Claim
19 words
The output protection circuit of claim 15, wherein said resistor has a resistance between 200 Ω and 10,000 Ω.
Claim 20
Dependent Claim
38 words
The output protection circuit of claim 15, wherein said resistor is a resistive circuit element chosen from the group consisting of a polysilicon resistor, a polycide resistor, a P + diffusion resistor, and an N + diffusion resistor.
Claim 21
Dependent Claim
49 words
The output protection circuit of claim 15, wherein said resistor forms an RC low pass filter in conjunction with intrinsic capacitance present at said gate of said second PMOS transistor; said low pass filter preventing said second PMOS transistor from being turned on by transients coupled through said resistor.
Claim 22
Dependent Claim
50 words
The output protection circuit of claim 15, wherein the CMOS output buffer device further includes an input buffer having an input lead coupled to said output pad, and an output lead; whereby the output protection circuit also protects the input buffer from a positive ESD potential at said output pad.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-03 | 1996-11-02 | 1997-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-03 | 2000-11-02 | 2001-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-03 | 2004-11-02 | 2005-05-04 | $7700.00 | Window Closed / Lapsed |