US5206825A
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US
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Arithmetic processor using signed-digit representation of external operands
Assignee: Panasonic Holdings Corp
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Filing: 1992-03-24
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Granted: 1993-04-27
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Expires: 2012-03-24
Abstract
Abstract This an arithmetic processor which represents internal arithmetic operands as signed-digit numbers, each digit of which may have either positive, zero, or negative values and which executes addition of a plurality of numbers each of whose most significant digit is offset with respect to the other numbers. The arithmetic processor includes an adder tree which is so constituted that a pair of said plurality of numbers are added to obtain a partial sum and further pairs of partial sums are successively added to obtain a final sum of all numbers. The arithmetic processor further comprises first means for adding a portion of the two numbers where both digits are present, second means for causing a lower order portion where only one of the numbers has a digit present to directly become part of the sum, third means for retaining or outputting a carry created by the first means, and fourth means for adding the carry created in each add stage of the adder tree to the later add stages of the adder tree to obtain the sum.
Inventors
- 👤 Naofumi Takagi
- 👤 Tsuguyasu Hatsuda
- 👤 Toru Kakiage
- 👤 Takashi Taniguchi
- 👤 Tamotsu Nishiyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:20
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/535; G06F7/4824; G06F7/537; G06F7/5375
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
171 words
An adder circuit for use in an adder tree having a plurality of adder stages that generate a partial sum from the addition of an augend and an addend, said augend and addend being represented as signed-digit numbers which have an overlapping portion wherein digits of said augend overlap digits of said addend and first and second non-overlapping portions caused by the augend being offset with respect to said addend, wherein said first non-overlapping portion contains only higher order digits of said addend and said second non-overlapping portion contains only lower order digits of said augend, said adder circuit comprising logic circuitry for adding the digits of said augend and addend in said overlapping portion to generate part of said partial sum for application to an adder in a subsequent adder stage, generating a carry resulting from the addition of the highest order digits of said overlapping portion, and directly applying the digits in the first non-overlapping portion to said subsequent adder stage to form part of the partial sum therein.
Claim 2
Dependent Claim
171 words
An adder circuit for use in an adder tree having a plurality of adder stages that generate a partial sum from the addition of an augend and an addend, said augend and addend being represented as signed-digit numbers which have an overlapping portion wherein digits of said augend overlap digits of said addend and first and second non-overlapping portions caused by the augend being offset with respect to said addend, wherein said first non-overlapping portion contains only higher order digits of said addend and said second non-overlapping portion contains only lower order digits of said augend, said adder circuit comprising logic circuitry for adding the digits of said augend and addend in said overlapping portion to generate part of said partial sum for application to an adder in a subsequent adder stage, generating a carry resulting from the addition of the highest order digits of said overlapping portion, and directly applying the digits in the first non-overlapping portion to said subsequent adder stage to form part of the partial sum therein.
Claim 3
Dependent Claim
230 words
In an arithmetic processor having an adder tree that generates a final sum of a plurality of numbers, each of which is internally represented as a signed-digit number, said adder tree having a plurality of intermediate adder stages and a final adder stage, each adder stage having one or more adders for adding an augend and addend pair, each pair being one of said plurality of numbers or a partial sum obtained as the result of an addition in a preceding intermediate adder stage, said augend and addend pair having an overlapping portion wherein the digits of said augend overlap digits of said addend and first and second non-overlapping portions caused by the augend being offset with respect to said addend wherein said first non-overlapping portion contains only higher order digits of said addend and said second non-overlapping portion contains only lower order digits of said augend, each of said intermediate adder stages including one or more adders comprising logic circuitry for adding the digits of said augend and addend in said overlapping portion to generate part of said partial sum for application to an adder in a subsequent adder stage, generating a carry resulting from the addition of the highest order digits of said overlapping portion, and directly applying the digits in the first non-overlapping portion to said subsequent adder stage to form part of the partial sum therein.
Claim 4
Dependent Claim
230 words
In an arithmetic processor having an adder tree that generates a final sum of a plurality of numbers, each of which is internally represented as a signed-digit number, said adder tree having a plurality of intermediate adder stages and a final adder stage, each adder stage having one or more adders for adding an augend and addend pair, each pair being one of said plurality of numbers or a partial sum obtained as the result of an addition in a preceding intermediate adder stage, said augend and addend pair having an overlapping portion wherein the digits of said augend overlap digits of said addend and first and second non-overlapping portions caused by the augend being offset with respect to said addend wherein said first non-overlapping portion contains only higher order digits of said addend and said second non-overlapping portion contains only lower order digits of said augend, each of said intermediate adder stages including one or more adders comprising logic circuitry for adding the digits of said augend and addend in said overlapping portion to generate part of said partial sum for application to an adder in a subsequent adder stage, generating a carry resulting from the addition of the highest order digits of said overlapping portion, and directly applying the digits in the first non-overlapping portion to said subsequent adder stage to form part of the partial sum therein.
Claim 5
Independent Claim
185 words
A method for configuring an adder tree having a plurality of adder stages that each generate a partial sum from the addition of an augend and addend, said augend and addend being represented as signed-digit numbers arranged to have an overlapping portion wherein digits of said augend overlap digits of said addend and first and second non-overlapping portions caused by the augend being offset with respect to said addend wherein said first non-overlapping portion contains only higher order digits of said addend and said second non-overlapping portion contains only lower order digits of said augend, said method comprising the steps of: a) providing adder circuitry for adding the digits of said augend and said addend in said overlapping portion to generate part of said partial sum for application to an adder in a subsequent adder stage; b) providing circuitry for outputting a carry bit resulting from the addition of the highest order digits of said overlapping portion; and c) providing circuitry for directly applying all the digits in said first non-overlapping portion to said subsequent adder stage to form part of the partial sum therein.
Claim 6
Independent Claim
185 words
A method for configuring an adder tree having a plurality of adder stages that each generate a partial sum from the addition of an augend and addend, said augend and addend being represented as signed-digit numbers arranged to have an overlapping portion wherein digits of said augend overlap digits of said addend and first and second non-overlapping portions caused by the augend being offset with respect to said addend wherein said first non-overlapping portion contains only higher order digits of said addend and said second non-overlapping portion contains only lower order digits of said augend, said method comprising the steps of: a) providing adder circuitry for adding the digits of said augend and said addend in said overlapping portion to generate part of said partial sum for application to an adder in a subsequent adder stage; b) providing circuitry for outputting a carry bit resulting from the addition of the highest order digits of said overlapping portion; and c) providing circuitry for directly applying all the digits in said first non-overlapping portion to said subsequent adder stage to form part of the partial sum therein.
Claim 7
Dependent Claim
147 words
An arithmetic processor which operates on an internal operand expressed as a signed-digit number, said arithmetic processor representing each digit of a first portion of said internal operand by a first set of electrical multi-bit signals chosen in accordance with one of a plurality of encoding rules which define the multiple ways of expressing a digit of a signed-digit number by multi-bit electrical signals, said arithmetic processor further representing each digit of a second portion of said internal operand by a second set of electrical multi-bit signals chosen in accordance with another of said plurality of encoding rules, said arithmetic processor having a first circuit for arithmetically processing said first set of multi-bit electrical signals corresponding to the first portion of said internal operand and a second circuit for arithmetically processing the second set of multi-bit electrical signals corresponding to the second portion of said internal operand.
Claim 8
Dependent Claim
147 words
An arithmetic processor which operates on an internal operand expressed as a signed-digit number, said arithmetic processor representing each digit of a first portion of said internal operand by a first set of electrical multi-bit signals chosen in accordance with one of a plurality of encoding rules which define the multiple ways of expressing a digit of a signed-digit number by multi-bit electrical signals, said arithmetic processor further representing each digit of a second portion of said internal operand by a second set of electrical multi-bit signals chosen in accordance with another of said plurality of encoding rules, said arithmetic processor having a first circuit for arithmetically processing said first set of multi-bit electrical signals corresponding to the first portion of said internal operand and a second circuit for arithmetically processing the second set of multi-bit electrical signals corresponding to the second portion of said internal operand.
Claim 9
Dependent Claim
162 words
An arithmetic processor utilizing signed-digit internal operands for generating a plurality of partial remainders and determining therefrom a quotient resulting from the division of a dividend by a divisor, said arithmetic processor representing higher order digits of said partial remainders which are used to determine a digit of said quotient by a first set of electrical multi-bit signals chosen in accordance with one of a plurality of encoding rules which define the multiple ways of expressing a digit of a signed-digit number by multi-bit electrical signals, said arithmetic processor representing each of the remaining digits of said partial remainders by a second set of electrical multi-bit signals chosen in accordance with another of said plurality of encoding rules, said arithmetic processor having a first circuit for arithmetically processing said first set of multi-bit electrical signals to determine a digit of said quotient and a second circuit for arithmetically processing the second set of multi-bit electrical signals to determine a subsequent partial remainder.
Claim 10
Dependent Claim
162 words
An arithmetic processor utilizing signed-digit internal operands for generating a plurality of partial remainders and determining therefrom a quotient resulting from the division of a dividend by a divisor, said arithmetic processor representing higher order digits of said partial remainders which are used to determine a digit of said quotient by a first set of electrical multi-bit signals chosen in accordance with one of a plurality of encoding rules which define the multiple ways of expressing a digit of a signed-digit number by multi-bit electrical signals, said arithmetic processor representing each of the remaining digits of said partial remainders by a second set of electrical multi-bit signals chosen in accordance with another of said plurality of encoding rules, said arithmetic processor having a first circuit for arithmetically processing said first set of multi-bit electrical signals to determine a digit of said quotient and a second circuit for arithmetically processing the second set of multi-bit electrical signals to determine a subsequent partial remainder.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-26 | 1996-10-26 | 1997-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-26 | 2000-10-26 | 2001-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-26 | 2004-10-26 | 2005-04-27 | $7700.00 | Window Closed / Lapsed |