Method and apparatus for optimized processing of sparse matrices

Claim 2

A computer architecture for processing a sparse matrix, comprising: a memory that stores a value-row vector corresponding to nonzero values of said sparse matrix, where each of said nonzero values is located at a defined row and column position in said sparse matrix, said value-row vector including a first vector including nonzero values of said sparse matrix and delimiting characters indicating a transition from one of said columns to another of said columns, and a second vector defining row position values of said sparse matrix corresponding to said nonzero values in said first vector and column position values in said sparse matrix corresponding to the column position of said nonzero values in said first vector; a circuit, coupled to said memory, to detect said delimiting characters within said value-row vector; and a multiplier, coupled to said memory and sad circuit, to execute matrix-vector multiplication on said value-row vector from said memory.

Claim 3

The apparatus of claim 1 wherein said multiplier performs said matrix-vector multiplication by multiplying an indexed value of said first vector value by a column value from a second matrix to form a matrix-vector product which is added to a previous matrix-vector product.

Claim 4

A computer architecture for processing a sparse matrix comprising: means for storing a value-row vector corresponding to nonzero values of said sparse matrix composed of a plurality of columns and rows; a first vector fetch unit for receiving from said storing means row values and column values from said value-row vector; a second vector fetch unit for receiving from said storing means a matrix value from said value-row vector; a special character detection device, coupled to said second vector fetch unit, for detecting a special character in said matrix value; a latch coupled to said first vector fetch unit for receiving a column value from said first vector fetch unit and for latching a corresponding latched vector element of a first defined vector; a floating point multiplier, coupled to said latch and said second vector fetch unit, for multiplying said matrix value from said second vector fetch unit with said latched vector element to form a multiplier product; a cache storing at least a portion of a second defined vector and outputing an element of said second defined vector corresponding to a row value from said first vector; and a floating point adder for adding said multiplier product and said second vector element output by said cache.

Claim 5

A computer architecture for processing a sparse matrix comprising: means for storing a value-row vector corresponding to nonzero values of said sparse matrix composed of a plurality of columns and rows; a first vector fetch unit for receiving from said storing means row values and column values from said value-row vector; a second vector fetch unit for receiving from said storing means a matrix value from said value-row vector; a special character detection device, coupled to said second vector fetch unit, for detecting a special character in said matrix value; a latch coupled to said first vector fetch unit for receiving a column value from said first vector fetch unit and for latching a corresponding latched vector element of a first defined vector; a floating point multiplier, coupled to said latch and said second vector fetch unit, for multiplying said matrix value from said second vector fetch unit with said latched vector element to form a multiplier product; a cache storing at least a portion of a second defined vector and outputing an element of said second defined vector corresponding to a row value from said first vector; and a floating point adder for adding said multiplier product and said second vector element output by said cache.

Claim 6

The apparatus of claim 3 wherein said value-row vector includes a K vector including said value and delimiting characters indicating a transition from one of said columns to another of said columns; and an R vector defining said row value and column difference values corresponding to the difference between two of said columns which include said nonzero data.

Claim 7

The apparatus of claim 4 wherein said special character detection device is a CMOS zero detection circuit.

Claim 8

The apparatus of claim 4 wherein said cache utilizes a pipelined one-cycle write.

Claim 9

The apparatus of claim 6 wherein said cache receives a cache line including a tag, multi-bit data, a valid-bit, and a dirty-bit.

Claim 10

The apparatus of claim 7 wherein said pipelined one-cycle write includes a first stage to compare a first tag of a first cache line to a second tag of a second cache line and a second stage to perform a write operation when said first tag and said second tag match.

Claim 11

The apparatus of claim 8 wherein said write operation is to cache alone and not to a secondary memory.

Claim 12

The apparatus of claim 9 further comprising: means for prefetching said R vector.

Claim 13

The apparatus of claim 10 wherein said prefetching means includes: memory means coupled to said first vector fetch unit for storing addresses to be used if a cache miss occurs; a controller coupled to said memory means and said cache; a hit queue coupled to said memory; a miss queue coupled to a primary memory; and a multiplexer with inputs coupled to said hit queue and said miss queue and an output coupled to said floating point adder.

Claim 14

The apparatus of claim 4, wherein said apparatus is utilized as a coprocessor.

Claim 15

The apparatus of claim 3 further comprising an indexing circuit that determines the row and column position of each sparse matrix value being multiplied by said multiplier, and fetches and supplies to said multiplier a corresponding multiplicand.

Claim 16

A computer architecture for processing a sparse matrix, comprising: a memory for storing a value-row vector corresponding to nonzero values of said sparse matrix, where each of said nonzero values is located at a defined row and column position in said sparse matrix, said value-row vector including a first vector containing first vector values including nonzero values of said sparse matrix and special characters indicating a transition from one of said columns to another of said columns, and a second vector containing second vector values defining row position values of said sparse matrix corresponding to said nonzero values in said first vector and column position values in said sparse matrix corresponding to the column position of said nonzero values in said first vector; a floating point multiplier, coupled to said memory, for multiplying said nonzero values of said sparse matrix by an indexed column element value to produce a multiplier vector product; and a floating point adder, coupled to said floating point multiplier, for adding said multiplier vector product with a sum of prior multiplier vector products.

Claim 17

A computer architecture for processing a sparse matrix, comprising: a memory for storing a value-row vector corresponding to nonzero values of said sparse matrix, where each of said nonzero values is located at a defined row and column position in said sparse matrix, said value-row vector including a first vector containing first vector values including nonzero values of said sparse matrix and special characters indicating a transition from one of said columns to another of said columns, and a second vector containing second vector values defining row position values of said sparse matrix corresponding to said nonzero values in said first vector and column position values in said sparse matrix corresponding to the column position of said nonzero values in said first vector; a floating point multiplier, coupled to said memory, for multiplying said nonzero values of said sparse matrix by an indexed column element value to produce a multiplier vector product; and a floating point adder, coupled to said floating point multiplier, for adding said multiplier vector product with a sum of prior multiplier vector products.

Claim 18

The apparatus of claim 14 further comprising: a first vector fetch unit, coupled to said memory, to obtain said first vector values; and a second vector fetch unit, coupled to said memory, to obtain said second vector values.

Claim 19

The apparatus of claim 15 further comprising: a symbol identification circuit coupled to said first vector fetch unit to identify said special characters.

Claim 20

The apparatus of claim 16 further comprising: a latch coupled to said second vector fetch unit to receive said column position values from said second vector values, and for latching said indexed column element value into said multiplier.

Claim 21

The apparatus of claim 17 further comprising: a cache, coupled to said multiplier, for storing said prior multiplier vector products.

Claim 22

The apparatus of claim 16 wherein said symbol identification circuit is a zero detection circuit.