Patent US5206532A successfully refreshed from Google Patents.
US5206532A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Buried contact between polysilicon gate and diffusion area
Assignee: Micron Technology Inc
•
Filing: 1991-08-22
•
Granted: 1993-04-27
•
Expires: 2011-08-22
Abstract
Abstract A buried contact between the gate of a transistor device formed at the surface of a semiconductor substrate and a diffusion region formed in the surface of the substrate remote from the transistor device. The buried contact includes a polysilicon interconnect structure formed after shaping of the gate layer and the gate insulator. The polysilicon interconnect structure engages a side edge and an adjoining lower surface of the gate layer at a location where the gate insulator has been removed by isotropic etching from between the gate layer and the surface of the substrate. The polysilicon interconnect layer also contacts the surface of the substrate beneath an overhanging edge of the gate layer so as to form a surface current pathway interface. Below the surface current pathway interface a migration region is formed by heat-induced movement of ions from the gate layer through the polysilicon interconnect structure. The migration region extends laterally away from the gate layer to make contact with a remote diffusion region, thereby effecting with the polysilicon interconnect structure the desired buried contact.
Inventors
- 👤 Martin C. Roberts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:56
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/021; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
284 words
A buried contact between a polysilicon gate and a diffusion region of a first conductivity type, said polysilicon gate having both a bottom surface and a plurality of vertical sides above the bottom surface and being disposed on a first insulative layer on a substrate, said diffusion region being located in the surface of the substrate remote from the polysilicon gate, said buried contact comprising: (a) a polysilicon interconnect structure, having both a bottom surface and a plurality of vertical sides above the bottom surface, disposed both above the first insulative layer on the substrate and against at least one of said plurality of vertical sides of the gate and contacting both the surface of the substrate and the first insulative layer, said polysilicon interconnect structure contacting the surface of the substrate to define thereat a surface current pathway interface located at the surface of said substrate remote and separated from the diffusion region; (b) a migration region of the first conductivity type disposed in the surface of the substrate below and in contact with all of said surface current pathway interface, said migration region extending laterally from said surface current pathway interface away from the gate to contact the diffusion region; and (c) a second insulative layer disposed against at least one of said plurality of sides of said polysilicon interconnect structure remote from the gate, said second insulative layer contacting the surface of the substrate adjacent said surface current pathway interface to define thereat an insulator contact surface, said insulator contact surface including at least a portion of the boundary between said diffusion region and said migration region; wherein said surface current pathway interface and said insulator contact surface are substantially coplanar.
Claim 2
Dependent Claim
284 words
A buried contact between a polysilicon gate and a diffusion region of a first conductivity type, said polysilicon gate having both a bottom surface and a plurality of vertical sides above the bottom surface and being disposed on a first insulative layer on a substrate, said diffusion region being located in the surface of the substrate remote from the polysilicon gate, said buried contact comprising: (a) a polysilicon interconnect structure, having both a bottom surface and a plurality of vertical sides above the bottom surface, disposed both above the first insulative layer on the substrate and against at least one of said plurality of vertical sides of the gate and contacting both the surface of the substrate and the first insulative layer, said polysilicon interconnect structure contacting the surface of the substrate to define thereat a surface current pathway interface located at the surface of said substrate remote and separated from the diffusion region; (b) a migration region of the first conductivity type disposed in the surface of the substrate below and in contact with all of said surface current pathway interface, said migration region extending laterally from said surface current pathway interface away from the gate to contact the diffusion region; and (c) a second insulative layer disposed against at least one of said plurality of sides of said polysilicon interconnect structure remote from the gate, said second insulative layer contacting the surface of the substrate adjacent said surface current pathway interface to define thereat an insulator contact surface, said insulator contact surface including at least a portion of the boundary between said diffusion region and said migration region; wherein said surface current pathway interface and said insulator contact surface are substantially coplanar.
Claim 3
Dependent Claim
33 words
A buried contact as recited in claim 1, wherein said edge of the insulative layer comprises a side edge, and wherein said polysilicon interconnect structure contacts the side edge of the insulative layer.
Claim 4
Dependent Claim
35 words
A buried contact as recited in claim 2, wherein a portion of said polysilicon interconnect structure extends below the gate and contacts said side edge of the insulative layer upon which the gate is disposed.
Claim 5
Dependent Claim
43 words
A buried contact as recited in claim 1, wherein said gate comprises a side edge that overhangs said surface current pathway interface, and wherein said polysilicon interconnect structure is disposed against the side edge of the gate overhanging said surface current pathway interface.
Claim 6
Dependent Claim
28 words
A buried contact as recited in claim 1, wherein said polysilicon interconnect structure is disposed between the gate and the substrate at said edge of the insulative layer.
Claim 7
Dependent Claim
56 words
A buried contact as recited in claim 1, wherein said gate comprises a side edge that overhangs said surface current pathway interface, and wherein said polysilicon interconnect structure is disposed against the side edge of the gate overhanging said surface current pathway interface and against the bottom of the gate adjoining to said side edge thereof.
Claim 8
Dependent Claim
36 words
A buried contact as recited in claim 6, wherein said polysilicon interconnect structure comprises a generally orthogonally-shaped cross-section in a plane oriented normal the surface of the substrate and normal said side edge of said gate.
Claim 9
Dependent Claim
18 words
A buried contact as recited in claim 1, wherein said polysilicon interconnect structure is created by isotropic deposition.
Claim 10
Dependent Claim
50 words
A buried contact as recited in claim 1, wherein the gate is of the first conductivity type, and wherein said migration region is formed by diffusion of carriers of a first conductivity type from the gate through said polysilicon interconnect structure into the substrate at said surface current pathway interface.
Claim 11
Dependent Claim
35 words
A buried contact as recited in claim 1, wherein the gate is the gate of a first transistor device and the diffusion region is one of the source and drain of a second transistor device.
Claim 12
Dependent Claim
21 words
A buried contact as recited in claim 10, wherein said first and second transistor devices are cross-coupled at the gates thereof.
Claim 13
Dependent Claim
19 words
A buried contact as recited in claim 11, wherein said first and second transistors comprise a binary flip-flop circuit.
References Cited (Backward Citations)
US4413402A
Cited
US4939104A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-26 | 1996-10-26 | 1997-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-26 | 2000-10-26 | 2001-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-26 | 2004-10-26 | 2005-04-27 | $7700.00 | Window Closed / Lapsed |