Method and apparatus for resetting a memory upon power recovery

Claim 2

In a data processing system including a memory for storing data, a power system for providing power to the data processing system, a battery back-up means for providing power to certain of the data processing system circuitry during power system interrupts when the power system is not providing power to the data processing system, and a system manager means for monitoring the power system and asserting a system reset signal when the power system provides power to the data processing system at initial system start-up and upon restoration of power from the power system to the data processing system after a power system interrupt, the memory including memory elements for storing the data and a memory controller including a memory control means for providing memory control signals for controlling operations of the memory and a refresh means including for providing refresh signals to the memory elements, the refresh means including a refresh clock for providing a refresh clock signal indicating refresh clock cycles and a refresh counter connected from the refresh clock and responsive to the refresh clock signal for counting refresh clock cycles and providing refresh signals corresponding to the refresh clock cycles to the memory elements, the memory control means of the memory controller being connected from the power system and the memory elements and the refresh means of the memory controller being connected from the power system and from the battery back-up means, means for resetting the memory controller so that the memory control signals provided by the memory control means of the memory controller are in synchronization with the refresh signals provided by the refresh means when the power system provides power to the data processing system at initial system start-up and upon restoration of power from the power system to the data processing system after a power system interrupt, comprising: state detection means connected from the refresh counter for detecting a change in count of the refresh counter to a count equivalent to a reset count of the refresh counter and asserting a state change signal, and memory controller reset means connected from the state detection means and connected from the system manager means and responsive to the state change signal and to the occurrence of the system reset signal for providing a memory controller reset signal to the memory controller, whereby the memory controller reset signal occurs in synchronization with the change of count of the refresh counter to the count equivalent to the refresh counter reset count, and the memory controller is responsive to the memory controller reset signal so that the memory control signals provided by the memory control means of the memory controller are in synchronization with the refresh signals provided by the refresh means.

Claim 3

The memory reset means of claim 1, further comprising: a time-out clock means for providing a time-out clock signal indicating time-out clock cycles, a time-out counter means connected from the time-out clock means and connected from the system manager means for counting time-out clock cycles and responsive to the assertion of the reset signal and responsive to the time-out clock signal for counting time-out clock after the system reset signal has been asserted, a time-out period detection means connected from the time-out counter means and responsive to the count of time-out clock cycles in the time-out counter means after the reset signal has been asserted for providing a time out signal when the time-out counter has counted a memory refresh period plus one time-out clock cycle, wherein a memory refresh period is the number of refresh clock cycles required to refresh each of the memory elements, and a time-out detection means connected from the time-out period detection means and from the state detection means and having a memory controller reset signal output connected to the memory controller, the time-out detection means being responsive to the time-out signal and to the state change signal for providing a time-out reset signal to the memory control means and the refresh means of the memory controller when the state change signal has not been asserted during the period after the system reset signal has been asserted and the time-out counter has counted a refresh period plus one time-out clock cycle, whereby the memory control means and the refresh means of the memory controller are connected from the time-out reset signal provided by the time-out detection means and are responsive to the memory controller reset signal provided by the time-out detection means so that the memory control means and the refresh means of the memory controller are reset and the memory control means and the refresh means of the memory controller are in synchronization with the refresh clock signal.

Claim 4

In a data processing system including a memory for storing data, a power system for providing power to the data processing system, a battery back-up means for providing power to certain of the data processing system circuitry during power system interrupts when the power system is not providing power to the data processing system, and a system manager means for monitoring the power system and asserting a system reset signal when the power system provides power to the data processing system at initial system start-up and upon restoration of power from the power system to the data processing system after a power system interrupt, the memory including memory elements for storing the data and a memory controller including a memory control means for providing memory control signals for controlling operations of the memory and a refresh means including for providing refresh signals to the memory elements, the refresh means including a refresh clock for providing a refresh clock signal indicating refresh clock cycles and a refresh counter connected from the refresh clock and responsive to the refresh clock signal for counting refresh clock cycles and providing refresh signals corresponding to the refresh clock cycles to the memory elements, the memory control means of the memory controller being connected from the power system and the memory elements and the refresh means of the memory controller being connected from the power system and from the battery back-up means, a method for resetting the memory controller so that the memory control signals provided by the memory control means of the memory controller are in synchronization with the refresh signals provided by the refresh means when the power system provides power to the data processing system at initial system start-up and upon restoration of power from the power system to the data processing system after a power system interrupt, comprising the steps of: in state detection means connected from the refresh counter, detecting a change in count of the refresh counter to a count equivalent to a reset count of the refresh counter and asserting a state change signal, and in a memory controller reset means connected from the state detection means and connected from the system manager means and responsive to the state change signal and to the occurrence of the system reset signal, providing a memory controller reset signal to the memory controller, whereby the memory controller reset signal occurs in synchronization with the change of count of the refresh counter to the count equivalent to the refresh counter reset count, and the memory controller is responsive to the memory controller reset signal so that the memory control signals provided by the memory control means of the memory controller are in synchronization with the refresh signals provided by the refresh means.

Claim 5

In a data processing system including a memory for storing data, a power system for providing power to the data processing system, a battery back-up means for providing power to certain of the data processing system circuitry during power system interrupts when the power system is not providing power to the data processing system, and a system manager means for monitoring the power system and asserting a system reset signal when the power system provides power to the data processing system at initial system start-up and upon restoration of power from the power system to the data processing system after a power system interrupt, the memory including memory elements for storing the data and a memory controller including a memory control means for providing memory control signals for controlling operations of the memory and a refresh means including for providing refresh signals to the memory elements, the refresh means including a refresh clock for providing a refresh clock signal indicating refresh clock cycles and a refresh counter connected from the refresh clock and responsive to the refresh clock signal for counting refresh clock cycles and providing refresh signals corresponding to the refresh clock cycles to the memory elements, the memory control means of the memory controller being connected from the power system and the memory elements and the refresh means of the memory controller being connected from the power system and from the battery back-up means, a method for resetting the memory controller so that the memory control signals provided by the memory control means of the memory controller are in synchronization with the refresh signals provided by the refresh means when the power system provides power to the data processing system at initial system start-up and upon restoration of power from the power system to the data processing system after a power system interrupt, comprising the steps of: in state detection means connected from the refresh counter, detecting a change in count of the refresh counter to a count equivalent to a reset count of the refresh counter and asserting a state change signal, and in a memory controller reset means connected from the state detection means and connected from the system manager means and responsive to the state change signal and to the occurrence of the system reset signal, providing a memory controller reset signal to the memory controller, whereby the memory controller reset signal occurs in synchronization with the change of count of the refresh counter to the count equivalent to the refresh counter reset count, and the memory controller is responsive to the memory controller reset signal so that the memory control signals provided by the memory control means of the memory controller are in synchronization with the refresh signals provided by the refresh means.

Claim 6

The method of claim 3 for resetting memory state when power is applied to the system, further comprising the steps of: by operation of a time-out clock means, providing a time-out clock signal indicating time-out clock cycles, in a time-out counter means connected from the time-out clock means and connected from the system manager means and responsive to the assertion of the system rest signal and to the time-out clock signal, counting time-out clock cycles after the system reset signal has been asserted, in a time-out period detection means connected from the time-out counter means and responsive to the count of time-out clock cycles in the time-out counter means after the reset signal has been asserted, providing a time out signal when the time-out counter has counted a memory refresh period plus one time-out clock cycle, wherein a memory refresh period is the number of refresh clock cycles required to refresh each of the memory elements, and in a time-out detection means connected from the time-out period detection means and from the state detection means and having a time-out reset signal output connected to the memory control means and the refresh means of the memory controller, the time-out detection means being responsive to the time-out signal and to the state change signal, providing a memory controller reset signal to the memory control means and the refresh means of the memory controller when the state change signal has not been asserted during the period after the system reset signal has been asserted and the time-out counter has counted a refresh period plus one time-out clock cycle, whereby the memory control means and the refresh means of the memory controller are connected from the time-out reset signal provided by the time-out detection means and are responsive to the memory controller reset signal provided by the time-out detection means so that the memory control means and the refresh means of the memory controller are reset and the memory control means and the refresh means of the memory controller are in synchronization with the refresh clock signal.