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US5204935A
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Programmable fuzzy logic circuits
Assignee: Fujifilm Business Innovation Corp
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Filing: 1992-04-10
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Granted: 1993-04-20
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Expires: 2012-04-10
Abstract
Abstract A fuzzy logic circuit for operating a fuzzy logic with "fuzziness" taken into account has an operation section memory unit in which the result of operation to be outputted in response to an input is stored in an address specified by the input, the result of operation being rewritable, whereby the change in the contents of a fuzzy logic operation to be performed can be handled merely by rewriting the contents of the operation section memory unit.
Inventors
- 👤 Tohru Mihara
- 👤 Mitsumasa Narahara
- 👤 Yasunao Misawa
- 👤 Yasuo Wakamori
- 👤 Shinichi Yasunaga
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:34
CPC Classifications
G; G06; G06N; G06N7/00; G06N7/02; G06N7/04; Y; Y10; Y10S; Y10S706/00; Y10S706/90
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
196 words
A programmable fuzzy logic circuit, responsive to externally supplied input signals, comprising: logic operation result memory means for storing predetermined fuzzy logic operation results, said logic operation result memory means storing a plurality of sets of predetermined fuzzy logic operation results, each of said plurality of sets having different fuzzy logic operation results; operation section memory means for storing one of said sets of fuzzy logic operation results from the logic operation result memory means and for outputting as data said fuzzy logic operation results in accordance with the inputs signals; first input signal selection means, responsive to the input signals, for selecting one of a plurality of the input signals for use in writing data from said logic operation result memory means to said operation section memory means; memory writing means for writing one of said sets of fuzzy logic operation results into said operation section memory means at an address corresponding to the input signal selected by said first input signal selection means; and second input signal selection means, responsive to the input signals, for selecting one of a plurality of the input signals for controlling said operation section memory means to output data.
Claim 2
Dependent Claim
196 words
A programmable fuzzy logic circuit, responsive to externally supplied input signals, comprising: logic operation result memory means for storing predetermined fuzzy logic operation results, said logic operation result memory means storing a plurality of sets of predetermined fuzzy logic operation results, each of said plurality of sets having different fuzzy logic operation results; operation section memory means for storing one of said sets of fuzzy logic operation results from the logic operation result memory means and for outputting as data said fuzzy logic operation results in accordance with the inputs signals; first input signal selection means, responsive to the input signals, for selecting one of a plurality of the input signals for use in writing data from said logic operation result memory means to said operation section memory means; memory writing means for writing one of said sets of fuzzy logic operation results into said operation section memory means at an address corresponding to the input signal selected by said first input signal selection means; and second input signal selection means, responsive to the input signals, for selecting one of a plurality of the input signals for controlling said operation section memory means to output data.
Claim 3
Dependent Claim
19 words
A programmable fuzzy logic circuit as claimed in claim 1, further including a counter for supplying said input signals.
Claim 4
Dependent Claim
28 words
The programmable fuzzy logic circuit of claim 1, wherein the operation section memory means further comprises one of a random access memory, and a plurality of flip-flop circuits.
Claim 5
Dependent Claim
72 words
The programmable fuzzy logic circuit of claim 1, wherein the input signals supplied by said input signal supplying means are A bits long with a plurality of B high-order bits and a plurality of C low-order bits, wherein the high-order B bits are used as an address into said logic operation result memory means, and said low-order C bits are used as an address into said operation section memory means, wherein A=B+C.
Claim 6
Dependent Claim
21 words
The programmable fuzzy logic circuit of claim 1, wherein the operation section memory means further comprises an electrically erasable/programmable read-only memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-19 | 1996-10-19 | 1997-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-19 | 2000-10-19 | 2001-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-19 | 2004-10-19 | 2005-04-20 | $7700.00 | Window Closed / Lapsed |