Patent US5204864A successfully refreshed from Google Patents.
US5204864A
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US
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Multiprocessor bus debugger
Assignee: Northrop Grumman Corp
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Filing: 1990-08-16
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Granted: 1993-04-20
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Expires: 2010-08-16
Abstract
Abstract An arbiter circuit has a first flip flop and a second flip flop. The first flip flop sends a bus request (BR*) signal to the VME bus by toggling the bus request signal when a trigger signal is received. The second flip flop sends a bus busy (BBSY*) signal to the VME bus by toggling the bus busy signal when a bus grant (BG*) signal is received from the VME bus. The second flip flop releases the bus busy (BBSY*) signal on the VME bus when a reset is commanded at the end of the test by a controller or a push button switch. Tests are performed by writing to the bus and reading from the bus by an address register, a write data register and a read data register connected to the address and data lines of the VME bus. The trigger signal source is selected by a trigger select circuit. A data transfer acknowledge trigger can be selected to trigger every time the data transfer acknowledged (DTACK*) line from the VME bus indicates a data transfer on the bus. An external trigger can be selected where a particular trigger source, such as that selected by a moveable test probe, can be used as a trigger. An address trigger can be selected to trigger when the VME bus address matches a particular address. A trigger address can be selected to trigger when the VME bus address matches a particular address a specified number of times.
Inventors
- 👤 Chongsoo Won
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:58
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/221; G06F11/30; G06F11/34; G06F11/3466; G06F11/349; G06F11/348
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
88 words
An apparatus for seizing to allow testing over a multiprocessor bus, said apparatus comprising: a test probe receiving a trigger signal; a reset circuit commanding an end to a test: a first latch responsive to said test probe for toggling a bus request signal to the multiprocessor bus when said test probe receives the trigger signal; a second latch, responsive to said reset circuit and the multiprocessor bus, for toggling a bus busy signal to said multiprocessor bus when said reset circuit commands and end to the test.
Claim 2
Independent Claim
88 words
An apparatus for seizing to allow testing over a multiprocessor bus, said apparatus comprising: a test probe receiving a trigger signal; a reset circuit commanding an end to a test: a first latch responsive to said test probe for toggling a bus request signal to the multiprocessor bus when said test probe receives the trigger signal; a second latch, responsive to said reset circuit and the multiprocessor bus, for toggling a bus busy signal to said multiprocessor bus when said reset circuit commands and end to the test.
Claim 3
Dependent Claim
25 words
The apparatus of claim 1, wherein said second latch toggles the bus busy signal when a bus grant signal is received from the multiprocessor bus.
Claim 4
Dependent Claim
19 words
An apparatus according to claim 1, wherein said reset circuit comprises a reset switch connected to said second latch.
Claim 5
Independent Claim
89 words
An apparatus for seizing to allow testing over a multiprocessor bus, said apparatus comprising: a trigger source selector receiving and selecting a trigger signal; a reset circuit commanding an end to a test; an arbiter circuit, responsive to said trigger source selector, said reset circuit and the multiprocessor bus, for toggling a bus request signal to the multiprocessor bus when said trigger source selector receives the trigger signal and for toggling a bus busy signal to the multiprocessor bus when said reset circuit commands an end to the test.
Claim 6
Independent Claim
89 words
An apparatus for seizing to allow testing over a multiprocessor bus, said apparatus comprising: a trigger source selector receiving and selecting a trigger signal; a reset circuit commanding an end to a test; an arbiter circuit, responsive to said trigger source selector, said reset circuit and the multiprocessor bus, for toggling a bus request signal to the multiprocessor bus when said trigger source selector receives the trigger signal and for toggling a bus busy signal to the multiprocessor bus when said reset circuit commands an end to the test.
Claim 7
Dependent Claim
26 words
The apparatus according to claim 4, wherein said arbiter circuit toggles the bus busy signal when a bus grant signal is received from the multiprocessor bus.
Claim 8
Dependent Claim
36 words
The apparatus according to claim 4, wherein said trigger source selector selects at least a data transfer acknowledge trigger from the multiprocessor bus whereby a trigger signal is supplied every time the multiprocessor bus is accessed.
Claim 9
Dependent Claim
50 words
An apparatus according to claim 4, further comprising: a keypad; a controller connected to said keypad, said trigger source selector or and said arbiter circuit, said controller comprising said reset circuit for commanding an end of a test; and an address register connected to address lines of the multiprocessor bus.
Claim 10
Dependent Claim
66 words
An apparatus according to claim 7, further comprising: a trigger address register storing a target address; and an address comparator, connected to said trigger source selector, address lines of the multiprocessor bus and said trigger address register, outputting a trigger to said trigger source selector when the target address in said trigger address register coincides with an address on the address lines of the microprocessor bus.
Claim 11
Dependent Claim
31 words
An apparatus according to claim 7, further comprising a counter, connected to said trigger source selector, to output a trigger to said trigger source selector when a predetermined count is obtained.
Claim 12
Dependent Claim
58 words
An apparatus according to claim 9, further comprising: a trigger address register storing a target address; and an address comparator, connected to said counter, said trigger address register and address lines of the multiprocessor bus, to increment said counter when data in said trigger address register coincide with an address on the address lines of the multiprocessor bus.
Claim 13
Dependent Claim
72 words
An apparatus according to claim 7, wherein said apparatus further comprises a write data register connected to data lines of the multiprocessor bus; and wherein said controller controls said write data register to write data in said write data register over the multiprocessor bus to an address indicated by said address register after said trigger source selector has received a trigger signal and said arbiter circuit has toggled the bus request signal.
Claim 14
Dependent Claim
64 words
An apparatus according to claim 7, further comprising a read data register connected to data lines of the multiprocessor bus, wherein said controller controls read data register to read data over data lines of the multiprocessor bus from an address indicated by said address register after said trigger source selector receives a trigger signal and said arbiter circuit has toggled said bus request signal.
Claim 15
Independent Claim
413 words
An apparatus for testing over a Versa Module Europa bus, said apparatus comprising: a trigger source selector selecting at least a data transfer acknowledge trigger, an external trigger, an address trigger and an address count trigger; a reset circuit comprising a reset switch commanding an end to a test; a first latch responsive to said trigger source selector and toggling a bus request signal to the VME bus when said trigger source selector receives the trigger signal; a second latch, responsive to said reset circuit and the VME bus, first toggling a bus busy signal when a bus grant signal is received from the VME bus and second toggling a bus busy signal when said reset circuit commands an end to the test; a keypad; a controller, connected to said keypad, said trigger source selector and said second latch, wherein said controller comprises said reset circuit for commanding an end of a test; an address register connected to address lines of the VME bus; a trigger address register storing a target address; an address comparator connected to said trigger address register and connected to address lines of the VME bus to output a trigger to said trigger source selector when the target address in said trigger address register coincides with an address on the address lines of the VME bus; a counter, connected to said address comparator, to count responsive to said address comparator when the target address in said trigger address register coincides with an address on the address lines of the VME bus; a comparator, connected to said counter and a trigger address counter register, to output a trigger to said trigger source selector when a predetermined count is obtained; a write data register connected to data lines of the VME bus wherein said write data register writes data in said write data register over the VME bus to an address indicated by said address register after said trigger source selector receives a trigger signal and said first and second latches, have toggled said bus request signal; a read data register connected to said data lines of the VME bus wherein said read data register reads data over data lines of the VME bus from an address indicated by said address register after said trigger source selector receives a trigger signal and said first latch has toggled said bus request signal; and a display connected to at least said read data register to display the data in said read data register.
Claim 16
Independent Claim
413 words
An apparatus for testing over a Versa Module Europa bus, said apparatus comprising: a trigger source selector selecting at least a data transfer acknowledge trigger, an external trigger, an address trigger and an address count trigger; a reset circuit comprising a reset switch commanding an end to a test; a first latch responsive to said trigger source selector and toggling a bus request signal to the VME bus when said trigger source selector receives the trigger signal; a second latch, responsive to said reset circuit and the VME bus, first toggling a bus busy signal when a bus grant signal is received from the VME bus and second toggling a bus busy signal when said reset circuit commands an end to the test; a keypad; a controller, connected to said keypad, said trigger source selector and said second latch, wherein said controller comprises said reset circuit for commanding an end of a test; an address register connected to address lines of the VME bus; a trigger address register storing a target address; an address comparator connected to said trigger address register and connected to address lines of the VME bus to output a trigger to said trigger source selector when the target address in said trigger address register coincides with an address on the address lines of the VME bus; a counter, connected to said address comparator, to count responsive to said address comparator when the target address in said trigger address register coincides with an address on the address lines of the VME bus; a comparator, connected to said counter and a trigger address counter register, to output a trigger to said trigger source selector when a predetermined count is obtained; a write data register connected to data lines of the VME bus wherein said write data register writes data in said write data register over the VME bus to an address indicated by said address register after said trigger source selector receives a trigger signal and said first and second latches, have toggled said bus request signal; a read data register connected to said data lines of the VME bus wherein said read data register reads data over data lines of the VME bus from an address indicated by said address register after said trigger source selector receives a trigger signal and said first latch has toggled said bus request signal; and a display connected to at least said read data register to display the data in said read data register.
Claim 17
Independent Claim
93 words
A method for testing over a multiprocessor bus, said method comprising the steps of: (a) selecting a trigger source by moving a movable test probe to electrically contact a position in a circuit; (b) toggling a bus request signal when the moveable test probe receives a trigger signal; (c) writing data to or reading data from the multiprocessor bus to debug the bus; (d) toggling the bus busy signal when a bus grant signal is received from the multiprocessor bus; and (e) toggling a bus busy signal when a reset command is detected.
Claim 18
Independent Claim
93 words
A method for testing over a multiprocessor bus, said method comprising the steps of: (a) selecting a trigger source by moving a movable test probe to electrically contact a position in a circuit; (b) toggling a bus request signal when the moveable test probe receives a trigger signal; (c) writing data to or reading data from the multiprocessor bus to debug the bus; (d) toggling the bus busy signal when a bus grant signal is received from the multiprocessor bus; and (e) toggling a bus busy signal when a reset command is detected.
Claim 19
Independent Claim
93 words
An apparatus for testing over a multiprocessor bus, said apparatus comprising: seizing means for seizing the multiprocessor bus in response to a trigger signal; and test means, responsive to said seizing means, for testing over the multiprocessor bus when said seizing means seizes the multiprocessor bus; wherein said test means reads from the multiprocessor bus to test the multiprocessor bus; wherein said seizing means comprises: a trigger source selector for selecting a trigger source for said trigger signal; and an arbiter circuit for seizing the multiprocessor bus in response to the trigger signal.
Claim 20
Independent Claim
93 words
An apparatus for testing over a multiprocessor bus, said apparatus comprising: seizing means for seizing the multiprocessor bus in response to a trigger signal; and test means, responsive to said seizing means, for testing over the multiprocessor bus when said seizing means seizes the multiprocessor bus; wherein said test means reads from the multiprocessor bus to test the multiprocessor bus; wherein said seizing means comprises: a trigger source selector for selecting a trigger source for said trigger signal; and an arbiter circuit for seizing the multiprocessor bus in response to the trigger signal.
Claim 21
Dependent Claim
53 words
The apparatus according to claim 15, wherein said arbiter circuit includes: a first latch to seize the multiprocessor bus by toggling a bus request signal to the multiprocessor bus; and a second latch to release the multiprocessor bus by toggling a bus busy signal to the multiprocessor bus when a reset is commanded.
Claim 22
Dependent Claim
26 words
The apparatus according to claim 16, wherein said second latch toggles the bus busy signal when a bus grant signal is received from the multiprocessor bus.
Claim 23
Dependent Claim
74 words
An apparatus according to claim 15, wherein said seizing means further comprises: an address register connected to address lines of the multiprocessor bus; a trigger address register; and an address comparator, connected to said select means, address lines of the multiprocessor bus and said trigger address register, to output a trigger to said select means when data in said trigger address register compare with an address on the address lines of the microprocessor bus.
Claim 24
Dependent Claim
78 words
An apparatus according to claim 15, wherein said seizing means further comprises: an address register connected to address lines of the multiprocessor bus; a write data register connected to data lines of the multiprocessor bus; wherein said write data register writes data in said write data register over the multiprocessor bus to an address indicated by said address register after said select means has received a trigger signal and said arbiter means has toggled the bus request signal.
Claim 25
Dependent Claim
71 words
An apparatus according to claim 15, further comprising: an address register connected to address lines of the multiprocessor bus; a read data register connected to data lines of the multiprocessor bus, wherein said read data register reads data over data lines of the multiprocessor bus from an address indicated by said address register after said select means receives a trigger signal and said arbiter means has toggled said bus request signal.
Claim 26
Dependent Claim
28 words
An apparatus according to claim 15, wherein said seizing means further comprises a counter to output a trigger to said select means when a predetermined count is obtained.
Claim 27
Dependent Claim
59 words
An apparatus according to claim 21, wherein said seizing means further comprises: a trigger address register; and an address comparator, connected to said counter, said trigger address register and address lines of the multiprocessor bus, to said counter to count when data in said trigger address register compare with an address on the address lines of the multiprocessor bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-19 | 1996-10-19 | 1997-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-19 | 2000-10-19 | 2001-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-19 | 2004-10-19 | 2005-04-20 | $7700.00 | Window Closed / Lapsed |