US5202968A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Expansion system
Assignee: Toshiba Corp
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Filing: 1991-09-10
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Granted: 1993-04-13
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Expires: 2011-09-10
Abstract
Abstract A cache LSI has an expansion pin which is set to "0" (GND) level or "1" (Vcc) level. A portion of a SET field of a cache directory is used as a field for selecting a cache LSI. Each cache LSI includes a determination circuit. The determination circuit performs a predetermined logical operation based on a level signal set at the expansion pin and a level signal of the cache selection field in the SET field, and determines whether or not an intra-chip is selected.
Inventors
- 👤 Kazuyuki Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 19:56
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0661; G06F12/08; G06F12/0802; G06F2212/00; G06F2212/60; G06F2212/601
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
122 words
A LSI semiconductor device selecting system, comprising: means for supplying an address to access a plurality of LSI semiconductor devices; a plurality of LSI semiconductor devices, connected to said address supplying means, each including: at least one expansion pin which is set to a predetermined static level, the expansion pin specifying the number of LSI semiconductor devices and LSI-selection-data in the address; and means, connected to said address supplying means and said pins, for performing a logical operation in accordance with contents of the address and the level of the expansion pin; means, connected to the performing means and the supplying means, for determining whether an LSI semiconductor device is selected in accordance with a result from said logical operation performing means.
Claim 2
Dependent Claim
122 words
A LSI semiconductor device selecting system, comprising: means for supplying an address to access a plurality of LSI semiconductor devices; a plurality of LSI semiconductor devices, connected to said address supplying means, each including: at least one expansion pin which is set to a predetermined static level, the expansion pin specifying the number of LSI semiconductor devices and LSI-selection-data in the address; and means, connected to said address supplying means and said pins, for performing a logical operation in accordance with contents of the address and the level of the expansion pin; means, connected to the performing means and the supplying means, for determining whether an LSI semiconductor device is selected in accordance with a result from said logical operation performing means.
Claim 3
Dependent Claim
152 words
A memory system which avoids selecting signal delays due to alternative selection of memory devices, comprising: at least one memory device including, means for receiving an address having logical information, and at least one expansion pin, each expansion pin set at a respective logical level; means for configuring the memory system by specifying the number of memory devices and memory-device-selection-data in the address by using the expansion pin; and wherein each memory device includes a means, coupled to the address receiving means and at the least one expansion pin, for performing a logical operation on the logical information of the memory-device-selection-data and the logical level of the at least one expansion pin to determine whether said memory device is being selected for a memory access operation, and said memory access operation is performed by said at least one memory device upon determination that said at least one memory device has been selected.
Claim 4
Dependent Claim
152 words
A memory system which avoids selecting signal delays due to alternative selection of memory devices, comprising: at least one memory device including, means for receiving an address having logical information, and at least one expansion pin, each expansion pin set at a respective logical level; means for configuring the memory system by specifying the number of memory devices and memory-device-selection-data in the address by using the expansion pin; and wherein each memory device includes a means, coupled to the address receiving means and at the least one expansion pin, for performing a logical operation on the logical information of the memory-device-selection-data and the logical level of the at least one expansion pin to determine whether said memory device is being selected for a memory access operation, and said memory access operation is performed by said at least one memory device upon determination that said at least one memory device has been selected.
Claim 5
Dependent Claim
28 words
A system according to claim 2, wherein the expansion pins is set to either a ground level (logic "0"level) or a power source voltage level (logic "1" level).
Claim 6
Dependent Claim
18 words
A system according to claim 2, wherein each of the memory devices is a cache LSI semiconductor device.
Claim 7
Dependent Claim
35 words
A system according to claim 4, wherein a cache directory for the cache LSI semiconductor devices includes a SET address field for designating grouped blocks, and said means for receiving which supplies the SET address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-12 | 1996-10-12 | 1997-04-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-12 | 2000-10-12 | 2001-04-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-12 | 2004-10-12 | 2005-04-13 | $7700.00 | Window Closed / Lapsed |