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US5202907A
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US
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Solid-state image sensor output mosfet amplifier with mosfet load
Assignee: Sony Corp
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Filing: 1992-06-03
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Granted: 1993-04-13
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Expires: 2012-06-03
Abstract
Abstract There is provided a solid-state image sensor which can optimize the I-V characteristics of MOS transistors on drive side and load side, and which can improve the sensitivity by maximizing the small-signal AC gain of a source follower amplifier. According to one embodiment of the invention, a CCD solid-state image sensor has a floating diffusion type charge detecting amplifier composed of at least one drive side MOS transistor and at least one load side MOS transistor. In a substrate of one conductivity type, there are formed two wells of the opposite conductivity type independently. The drive side MOS transistor is formed in the first well which is deeper from the top surface of the semiconductor substrate. The load side MOS transistor is formed in the shallower second well. It is possible to further improve the AC gain by depleting or neutralizing the first well for the drive MOS transistor, and at the same time neutralizing the second well for the load MOS transistor.
Inventors
- 👤 Kazuya Yonemoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 05:37
CPC Classifications
H; H10; H10F; H10F39/00; H10F39/10; H10F39/12; H10D; H10D44/00; H10D44/40; H10D44/45; H10D44/454; H10F39/15; H10F39/153
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
190 words
A solid-state imager comprising: a substrate layer of a first conductivity type in a semiconductor substrate; first and second wells of a second conductivity type formed in said substrate layer, said first and second wells both extending into said substrate from a top surface of said substrate; a pair of first drain and first source regions of the first conductivity type formed in the first well region; a pair of second drain and second source regions of the first conductivity type formed in the second well region; a first insulated gate electrode formed on said top surface of said substrate, said first gate electrode forming a drive side MOS transistor with said first drain and source regions; and a second insulated gate electrode formed on said top surface of said substrate, said second gate electrode forming a load side MOS transistor with said second drain and source regions, said drive side MOS transistor and said load side MOS transistor being connected to form a floating diffusion type output amplifier of said solid-state imager; wherein said first well is deeper from said top surface of said substrate than said second well.
Claim 2
Dependent Claim
190 words
A solid-state imager comprising: a substrate layer of a first conductivity type in a semiconductor substrate; first and second wells of a second conductivity type formed in said substrate layer, said first and second wells both extending into said substrate from a top surface of said substrate; a pair of first drain and first source regions of the first conductivity type formed in the first well region; a pair of second drain and second source regions of the first conductivity type formed in the second well region; a first insulated gate electrode formed on said top surface of said substrate, said first gate electrode forming a drive side MOS transistor with said first drain and source regions; and a second insulated gate electrode formed on said top surface of said substrate, said second gate electrode forming a load side MOS transistor with said second drain and source regions, said drive side MOS transistor and said load side MOS transistor being connected to form a floating diffusion type output amplifier of said solid-state imager; wherein said first well is deeper from said top surface of said substrate than said second well.
Claim 3
Dependent Claim
15 words
A solid-state imager according to claim 1 wherein said first well is depleted in potential.
Claim 4
Dependent Claim
15 words
A solid-state imager according to claim 2 wherein said second well is neutralized in potential.
Claim 5
Dependent Claim
31 words
A solid-state imager according to claim 1 wherein a junction between said first well and said substrate layer is located near an end of a depletion layer of said substrate layer.
Claim 6
Dependent Claim
18 words
A solid-state imager according to claim 1 wherein said first and second wells are both neutralized in potential.
Claim 7
Dependent Claim
39 words
A solid-state imager according to claim 1 further comprising a highly doped contact region of the second conductivity type for neutralizing said second well in potential, said highly doped contact region being formed in said second well, and grounded.
Claim 8
Dependent Claim
30 words
A solid-state imager according to claim 6 further comprising a highly doped contact region of the second conductivity type which is formed in said first well and which is grounded.
Claim 9
Dependent Claim
35 words
A solid-state imager according to claim 7 wherein said output amplifier comprises a floating diffusion and a source follower amplifier which is formed by said drive side MOS transistor and said load side MOS transistor.
Claim 10
Dependent Claim
77 words
A solid-state imager according to claim 8 wherein said source follower amplifier comprises an input terminal for receiving an input signal from said floating diffusion, an output terminal for delivering an output signal, said first source region of said drive side MOS transistor and said second drain region of said load side MOS transistor being both connected to said output terminal, said first gate electrode of said drive side MOS transistor being connected to said input terminal.
Claim 11
Dependent Claim
59 words
A solid-state imager according to claim 9 further comprising an interline CCD imaging section which comprises a horizontal shift register connected with said floating diffusion, a plurality of vertical shift registers each of which is connected with said horizontal shift register, and an array of photosensitive elements each of which is connected with one of said vertical shift register.
References Cited (Backward Citations)
US5068736A
Cited
US5029190A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-12 | 1996-10-12 | 1997-04-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-12 | 2000-10-12 | 2001-04-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-12 | 2004-10-12 | 2005-04-13 | $7700.00 | Window Closed / Lapsed |