US5202854A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory circuit
Assignee: NEC Corp
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Filing: 1991-09-05
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Granted: 1993-04-13
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Expires: 2011-09-05
Abstract
Abstract A semiconductor memory circuit includes bit lines, word lines, memory cells, transfer gates, a sense amplifier, a precharge circuit and a control section. The transfer gates between the bit lines and the sense amplifier are non-conductive during the standby state of the memory. For reading-out data from the memory cell, the transfer gates are made conductive and thereafter the potential of the word line for the memory cell to be selected is raised to its high level, so that the data stored in the memory cell is read out on the bit line. Then, after the transfer gates are made non-conductive, the sense amplifier is activated. In this way, the coupling noise occuring when the transfer gates are made conductive before the level of the word lines become high and the coupling noise occuring when the transfer gates are made non-conductive after the level of the word lines become high cancel each other and, as a result, the voltage loss in the reading out of data from the memory can be eliminated.
Inventors
- 👤 Hiroki Koike
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 20:05
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091; G11C7/00; G11C7/06; G11C7/065
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
346 words
A semiconductor memory circuit comprising: a first bit line and a second bit line; a plurality of first word lines and a plurality of second word lines; a plurality of first memory cells which are respectively connected to said first word lines and said first bit line and which communicate memory data with said first bit line when said first word lines are of a selecting level; a plurality of second memory cells which are respectively connected to said second word lines and said second bit line and which communicate memory data with said second bit line when said second word lines are of a selecting level; a first transfer gate and a second transfer gate whose each one end is correspondingly connected to each of said first bit line and said second bit line and which are switched ON and OFF in response to a transfer signal; a sense amplifier whose first and second input-output terminals are respectively and correspondingly connected to the other ends of said first and second transfer gates and which are activated for amplifying signals between said first and second input-output terminals when an activating signal is at an activate level; a precharge circuit which precharges said first and second input-output terminals of the sense amplifier to a predetermined level when a precharge signal is at an active level; and a control section which sets said transfer signal to its active level thereby turning said first and second transfer gates to their ON-states after said precharge signal has been changed from its active level to its non-active level, which sets a predetermined word line of said plurality of first and second word lines to its selecting level after said transfer signal has been changed to its active level, which sets said transfer signal to its non-active level thereby turning said first and second transfer gates to their OFF-states after said predetermined word line has been changed to its selecting level, and which sets said activating signal to its active level after said transfer signal has been changed to its non-active level.
Claim 2
Dependent Claim
346 words
A semiconductor memory circuit comprising: a first bit line and a second bit line; a plurality of first word lines and a plurality of second word lines; a plurality of first memory cells which are respectively connected to said first word lines and said first bit line and which communicate memory data with said first bit line when said first word lines are of a selecting level; a plurality of second memory cells which are respectively connected to said second word lines and said second bit line and which communicate memory data with said second bit line when said second word lines are of a selecting level; a first transfer gate and a second transfer gate whose each one end is correspondingly connected to each of said first bit line and said second bit line and which are switched ON and OFF in response to a transfer signal; a sense amplifier whose first and second input-output terminals are respectively and correspondingly connected to the other ends of said first and second transfer gates and which are activated for amplifying signals between said first and second input-output terminals when an activating signal is at an activate level; a precharge circuit which precharges said first and second input-output terminals of the sense amplifier to a predetermined level when a precharge signal is at an active level; and a control section which sets said transfer signal to its active level thereby turning said first and second transfer gates to their ON-states after said precharge signal has been changed from its active level to its non-active level, which sets a predetermined word line of said plurality of first and second word lines to its selecting level after said transfer signal has been changed to its active level, which sets said transfer signal to its non-active level thereby turning said first and second transfer gates to their OFF-states after said predetermined word line has been changed to its selecting level, and which sets said activating signal to its active level after said transfer signal has been changed to its non-active level.
Claim 3
Dependent Claim
37 words
A semiconductor memory circuit according to claim 1, which further comprises another precharge circuit which includes transistors having gates receiving said precharge signal and which applies a precharge voltage directly to said first and second bit lines.
References Cited (Backward Citations)
US4803664A
Cited
US4943944A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-12 | 1996-10-12 | 1997-04-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-12 | 2000-10-12 | 2001-04-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-12 | 2004-10-12 | 2005-04-13 | $7700.00 | Window Closed / Lapsed |