Multiprocessing system includes interprocessor encoding and decoding logic used for communication between two cards through reduced addressing lines

Claim 1

An apparatus for selecting one of a plurality of devices which are addressed using a first number of address lines in a computer system, the apparatus comprising: an interchangeable card, wherein the plurality of devices are located on said interchangeable card; a system board including a connector for receiving said interchangeable card and conducting signals between said system board and said interchangeable card; a bus located on said system board and including said first number of address lines; a processor located on said interchangeable card generating address signals for presentation on said first number of address lines; means for coupling said processor address signals to said first number of address lines, said processor address signals being conducted across said connector; means located on said system board and coupled to said bus receiving said first number of address lines for decoding said first number of address lines to produce a plurality of signals each representing selection of a device; means located on said system board and coupled to said bus and said means for decoding said first number of address lines for encoding said plurality of signals representing selection of a device into a set of addressing signals wherein each encoded value represents one of said devices and the number of signals in said set is less than said first number, said set of addressing signals being provided to said connector for conduction to said interchangeable card; means located on said interchangeable card and receiving said set of addressing signals after conduction across said connector for decoding said encoded set of addressing signals to produce a signal representing selection of a device; and means coupled to said encoded signal set decoding means and located on said interchangeable card for selecting the device using said selection signal.

Claim 2

An apparatus for selecting one of a plurality of devices which are addressed using a first number of address lines in a computer system, the apparatus comprising: an interchangeable card, wherein the plurality of devices are located on said interchangeable card; a system board including a connector for receiving said interchangeable card and conducting signals between said system board and said interchangeable card; a bus located on said system board and including said first number of address lines; a processor located on said interchangeable card generating address signals for presentation on said first number of address lines; means for coupling said processor address signals to said first number of address lines, said processor address signals being conducted across said connector; means located on said system board and coupled to said bus receiving said first number of address lines for decoding said first number of address lines to produce a plurality of signals each representing selection of a device; means located on said system board and coupled to said bus and said means for decoding said first number of address lines for encoding said plurality of signals representing selection of a device into a set of addressing signals wherein each encoded value represents one of said devices and the number of signals in said set is less than said first number, said set of addressing signals being provided to said connector for conduction to said interchangeable card; means located on said interchangeable card and receiving said set of addressing signals after conduction across said connector for decoding said encoded set of addressing signals to produce a signal representing selection of a device; and means coupled to said encoded signal set decoding means and located on said interchangeable card for selecting the device using said selection signal.

Claim 4

An apparatus for selecting one of a plurality of devices which are addressed using a first number of address lines in a computer system including a clock signal, two timing control signals, one indicating an address portion of a cycle and one indicating a data portion of a cycle, the two timing control signals being non-overlapping, and a signal indicative of write/read status, the apparatus comprising: means receiving the first number of address lines for decoding the first number of address lines to produce a plurality of signals each representing selection of a device; means coupled to said means for decoding the first number of address lines and to said data portion timing control signal for encoding said plurality of signals representing selection of a device into a set of addressing signals wherein each encoded value represents one of said devices and the number of signals in said set is less than said first number and for latching said set of addressing signals on assertion of said data portion timing control signal; means receiving the clock signal, the data portion timing control signal, and the write/read status indicating signal for asserting a write strobe signal a predetermined number of clock signal cycles after said data portion timing control signal is asserted during a write cycle; means coupled to said encoding means for decoding said latched, encoded set of addressing signals to produce a signal representing selection of a device; and means receiving said write strobe signal and said selection signal for producing a storage signal for use by the device.

Claim 5

An apparatus for selecting one of a plurality of devices which are addressed using a first number of address lines in a computer system including a clock signal, two timing control signals, one indicating an address portion of a cycle and one indicating a data portion of a cycle, the two timing control signals being non-overlapping, and a signal indicative of write/read status, the apparatus comprising: means receiving the first number of address lines for decoding the first number of address lines to produce a plurality of signals each representing selection of a device; means coupled to said means for decoding the first number of address lines and to said data portion timing control signal for encoding said plurality of signals representing selection of a device into a set of addressing signals wherein each encoded value represents one of said devices and the number of signals in said set is less than said first number and for latching said set of addressing signals on assertion of said data portion timing control signal; means receiving the clock signal, the data portion timing control signal, and the write/read status indicating signal for asserting a write strobe signal a predetermined number of clock signal cycles after said data portion timing control signal is asserted during a write cycle; means coupled to said encoding means for decoding said latched, encoded set of addressing signals to produce a signal representing selection of a device; and means receiving said write strobe signal and said selection signal for producing a storage signal for use by the device.