US5200712A
Expired / Lapsed
US
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Variable speed phase locked loop
Assignee: Zenith Electronics LLC
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Filing: 1991-12-26
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Granted: 1993-04-06
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Expires: 2011-12-26
Abstract
Abstract A variable speed phase locked loop includes a phase detector and a voltage controlled oscillator, the output of which is provided through a divider circuit to the phase detector. A plurality of delay elements and a decoder divide the period of the phase detector input signal into discrete portions for enabling a plurality of weighted current sources. The current sources are coupled to the phase detector and change its gain. In the locked condition with minimum phase error, the gain of the phase detector is at a minimum and is progressively increased to a maximum when the phase error is maximum.
Inventors
- 👤 Gopal K. Srivastava
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:03
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183; H03L7/08; H03L7/10; H03L7/107; H03L7/1077; H03L7/191
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
94 words
The method of operating a phase detector comprising: establishing a variable gain characteristic that varies from a minimum to a maximum for said phase detector; operating said phase detector in a phase locked loop with a gain determined by said variable gain characteristic such that when in a locked condition, the gain of said phase detector is at said minimum and when in an unlocked condition, the gain of said phase detector is at said maximum, said gain of said phase detector increasing with increasing displacement from said locked condition to said unlocked condition.
Claim 2
Independent Claim
94 words
The method of operating a phase detector comprising: establishing a variable gain characteristic that varies from a minimum to a maximum for said phase detector; operating said phase detector in a phase locked loop with a gain determined by said variable gain characteristic such that when in a locked condition, the gain of said phase detector is at said minimum and when in an unlocked condition, the gain of said phase detector is at said maximum, said gain of said phase detector increasing with increasing displacement from said locked condition to said unlocked condition.
Claim 3
Dependent Claim
39 words
The method of claim 1 wherein said variable gain characteristic is divided into discrete portions and further including: accessing said discrete portions of said variable gain characteristic as a function of the error signal in said phase locked loop.
Claim 4
Independent Claim
108 words
The method of operating a phase detector comprising: establishing a variable gain characteristic that varies from a minimum to a maximum for said phase detector; operating said phase detector in a phase locked loop with a gain determined by said variable gain characteristic such that the gain of said phase detector is at said minimum when the absolute value of the phase error is minimum, and the gain of said phase detector is at said maximum when the absolute value of the phase error is maximum, said gain of said phase detector increasing with increasing displacement from the minimum phase error condition to the maximum phase error condition.
Claim 5
Independent Claim
108 words
The method of operating a phase detector comprising: establishing a variable gain characteristic that varies from a minimum to a maximum for said phase detector; operating said phase detector in a phase locked loop with a gain determined by said variable gain characteristic such that the gain of said phase detector is at said minimum when the absolute value of the phase error is minimum, and the gain of said phase detector is at said maximum when the absolute value of the phase error is maximum, said gain of said phase detector increasing with increasing displacement from the minimum phase error condition to the maximum phase error condition.
Claim 6
Dependent Claim
42 words
The method of claim 3 wherein said variable gain characteristic is divided into discrete time portions and further including: accessing said discrete time portions of said variable gain characteristic as a function of the phase error signal in said phase locked loop.
Claim 7
Dependent Claim
113 words
A phase locked loop including: an oscillator; a source of reference signal; a source of input signal; a phase detector controlling the frequency of said oscillator as a function of the phase difference between said reference signal and said input signal; means coupling said input signal and said reference signal to said phase detector, said phase detector developing an error signal for controlling said oscillator; and means for providing a variable gain characteristic for said phase detector as a function of said error signal whereby the gain of said phase detector is minimized in the locked condition of said phase locked loop and maximized in the unlocked condition of said phase locked loop.
Claim 8
Dependent Claim
113 words
A phase locked loop including: an oscillator; a source of reference signal; a source of input signal; a phase detector controlling the frequency of said oscillator as a function of the phase difference between said reference signal and said input signal; means coupling said input signal and said reference signal to said phase detector, said phase detector developing an error signal for controlling said oscillator; and means for providing a variable gain characteristic for said phase detector as a function of said error signal whereby the gain of said phase detector is minimized in the locked condition of said phase locked loop and maximized in the unlocked condition of said phase locked loop.
Claim 9
Dependent Claim
19 words
The phase locked loop of claim 5 further including divider means coupled between said oscillator and said phase detector.
Claim 10
Dependent Claim
27 words
The phase locked loop of claim 6 wherein said divider means is programmable for enabling said phase locked loop to operate over a wide range of frequencies.
Claim 11
Dependent Claim
42 words
The phase locked loop of claim 6 wherein said variable gain means includes a plurality of current sources coupled to said phase detector for determining the gain thereof; and means for enabling said current sources as a function of said error signal.
Claim 12
Dependent Claim
41 words
The phase locked loop of claim 8 wherein said variable gain means further include a plurality of delay elements coupled to said oscillator and to said dividing means; and decoding means coupled to said delay elements for enabling said current sources.
References Cited (Backward Citations)
US4714899A
Cited
US4980653A
Cited
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