First and second digital rate converter synchronization device and method

Claim 2

A digital synchronization device for at least partially synchronizing at least first and second digital rate converters (DRCs), the first DRC having an input of at least some first digital sequence samples {x 1 (k)} sampled at a first sampling rate and the second DRC having an input of at least some second digital sequence samples {y 2 (n)} related to the first digital sequence samples and sampled at a second sampling rate different from the first sampling rate, wherein: the first DRC comprises at least: a first buffer, operably coupled to receive the first digital sequence samples {x 1 (k)}, for delaying and temporarily storing the first digital sequence samples {x 1 (k)}; a first digital resampler having at least a first delay unit, operably coupled to the first buffer, for shifting the first digital sequence samples into the first delay unit and for generating first output digital sequence samples {y 1 (n)} at substantially the second sampling rate utilizing a first selected sample timing in accordance with a first shift control signal m 1 (n) and a first desired normalized timing offset τ 1 (n); and a first variable delay generating unit having a normalized timing input Δτ 1 (n), Δτ 1 (n) being a first sampling time advance, and being operably coupled to the first digital resampler, for providing the first desired normalized timing offset τ 1 (n) and for providing the first shift control signal m 1 (n) determined from a previous normalized timing offset τ 1 (n-1); and the second DRC comprises at least: a second buffer, operably coupled to receive the second digital sequence samples {y 2 (n)} related to the first digital sequence samples {x 1 (k)}, for at least delaying and temporarily storing the second digital sequence samples {y 2 (n)} and providing the delayed, temporarily stored samples to a second digital resampler; a second digital resampler having at least a second delay unit, operably coupled to the second buffer and to a second variable delay generating unit, for shifting the second digital sequence samples into the second delay unit and for generating second output digital sequence samples {x 2 (n)} at substantially the first sampling rate utilizing a selected sample timing in accordance with a second desirable normalized timing offset τ 2 (k), and a second shifting control signal m 2 (n) from the second variable delay generating unit, the second variable delay generating unit having a normalized timing input Δτ 2 (k), Δτ 2 (k) being a second sampling time advance, and being operably coupled to the second digital resampler, for providing the second desired normalized timing offset τ 2 (k) and for providing the second shift control signal m 2 (n) determined from a previous normalized timing offset τ 2 (n-1), the second variable delay generating unit being operably coupled at least to the second digital resampler, for providing shift and timing information in accordance with a second sampling time advance Δτ 2 (k), such that timing differences between the first digital sequence samples and the second output digital sequence samples are substantially detected and variations in the timing differences are substantially reduced.

Claim 3

The device of claim 1, wherein Δτ 2 (k) is substantially equal to ρ, where ρ is a nominal rate-conversion ratio.

Claim 4

The device of claim 1, wherein Δτ 2 (k) is substantially equal to ρ 2 Δτ 1 (n), where ρ is a nominal rate-conversion ratio.

Claim 5

The device of claim 1, wherein the first sampling time advance Δρ 1 (n) is preselected by an external controller.

Claim 6

The device of claim 1, wherein the first sampling time advance Δτ 1 (n) is determined from a conversion ratio ρ such that Δτ 1 (n)=1/ρ.

Claim 7

The device of claim 1, wherein the first digital resampler further comprises at least a sample shifting unit for providing delayed first digital sequence samples having a first selected rate, a first predetermined number of subfilters, and a linear interpolator for selecting a second predetermined number of subfilter outputs for generating a desired sample.

Claim 8

The device of claim 1, further including one of: the second buffer being further operably coupled to the second variable delay generating unit for providing a first feedback signal for queue-depth monitoring; and an output buffer of the second DRC being operably coupled to the second variable delay generating unit for providing a second feedback signal for queue-depth monitoring; such that the second variable delay generating unit provides shifting and timing information utilizing at least queue-depth monitoring for monitoring a depth of at least one of: an output buffer of the second output digital sequence samples {x 2 (k)}, and an input buffer of the second digital sequence samples {y 2 (n)}.

Claim 9

The device of claim 7, wherein, for a desired queue-depth D and a selected buffer being one of: the input buffer of {y 2 (n)} and the output buffer of x 2 (k), where the second variable delay generating unit further provides for: A) where the queue depth of the selected output buffer is greater than D, generating the second output digital sequence samples {x 2 (k)} at a rate smaller than the first sampling rate; B) where the queue depth of the selected output buffer is less than D, generating the second output digital sequence samples {x 2 (k)} at a rate greater than the first sampling rate; C) where the queue depth of the selected input buffer is greater than D, generating the second output digital sequence samples {x 2 (k)} at a rate greater than the first sampling rate; and D) where the queue depth of the selected input buffer is less than D, generating the second output digital sequence samples {x 2 (k)} at a rate smaller than the first sampling rate.

Claim 10

The device of claim 1, further including at least a zero-crossing checking and resetting unit, operably coupled to the first variable delay generating unit and to the second variable delay generating unit, for zero-checking the normalized timing offset τ 1 (n), such that, for providing shifting and timing information for a first digital rate converter having a first conversion ratio ρ: the first digital rate converter is initialized to a normalized timing offset of τ init ; the second digital rate converter is initialized to a normalized timing offset of (1-ρτ init )modulo 1; and where zero-crossing occurs, the zero-crossing checking and resetting unit resets a second normalized timing offset τ 2 (k) to one of: substantially 1-ρτ 1 (n) where τ 1 (n) is close to zero (crossing from one-side); and substantially ρ[1-τ 1 (n)] where a normalized timing offset τ 1 (n) is near one (crossing from zero side).

Claim 11

A modem for at least one of: transmitting and receiving information, such that at least first and second digital rate converters (DRCs) are at least partially synchronized, the first DRC having an input of at least some first digital sequence samples {x 1 (k)} sampled at a first sampling rate and the second DRC having an input of at least some second digital sequence samples {y 2 (n)} related to the first digital sequence samples and sampled at a second sampling rate different from the first sampling rate, comprising at least: A) an encoder/modulator unit, operably coupled to receive information, for at least providing encoded/modulated information; B) a transmission filter unit, operably coupled to the encoder/modulator unit, for at least filtering the encoded/modulated information to provide first digital sequence samples in a transmission form, {x 1 (k)}; C) a digital synchronization unit, operably coupled to the transmission filter unit, for providing output samples {x 2 (k)} at least partially synchronized with {x 1 (k)}, wherein: the first DRC comprises at least: a first buffer, operably coupled to receive the first digital sequence samples {x 1 (k)}, for delaying and temporarily storing the first digital sequence samples {x 1 (k)}; a first digital resampler having at least a first delay unit, operably coupled to the first buffer, for shifting the first digital sequence samples into the first delay unit and for generating first output sequence samples {y 1 (n)} at substantially the second sampling rate utilizing a first selected sample timing in accordance with a first shift control signal m 1 (n) and a first desired normalized timing τ 1 (n); and a first variable delay generating unit having a normalized timing offset input Δτ 1 (n), Δτ 1 (n) being a first sampling time advance, and being operably coupled to the first digital resampler, for providing the first desired normalized timing offset τ 1 (n) and for providing the first shift control signal m 1 (n) determined from a previous normalized timing offset τ 1 (n-1); and the second DRC comprises at least: a second buffer, operably coupled to receive the second digital sequence samples {y 2 (n)} related to the first digital sequence samples {x 1 (k)}, for at least delaying and temporarily storing the second digital sequence samples {y 2 (n)} and providing the delayed, temporarily stored samples to a second digital resampler; a second digital resampler having at least a second delay unit, operably coupled to the second buffer and to a second variable delay generating unit, for shifting the second digital sequence samples into the second delay unit and for generating second output digital sequence samples {x 2 (n)} at substantially the first sampling rate utilizing a selected sample timing in accordance with a second desirable normalized timing offset τ 2 (k), and a second shifting control signal m 2 (n) from the second variable delay generating unit, the second variable delay generating unit having a normalized timing input Δτ 2 (k), Δτ 2 (k) being a second sampling time advance, and being operably coupled to the second digital resampler, for providing the second desired normalized timing offset τ 2 (k) and for providing the second shift control signal m 2 (n) determined from a previous normalized timing offset τ 2 (n-1), the second variable delay generating unit being operably coupled at least to the second digital resampler, for providing shift and timing information in accordance with a second sampling time advance Δτ 2 (k), adjustment to the second variable delay generating unit further being provided by at least one of the following: a) one of: the second buffer being further operably coupled to the second variable delay generating unit for providing a first feedback signal for queue-depth monitoring; and an output buffer of the second DRC being operably coupled to the second variable delay generating unit for providing a second feedback signal for queue-depth monitoring; such that the second variable delay generating unit provides shifting and timing information utilizing at least queue-depth monitoring for monitoring a depth of at least one of: an output buffer of the second output digital sequence samples {x 2 (k)}, and an input buffer of the second digital sequence samples {y 2 (n)}; and b) at least a zero-crossing checking and resetting unit, operably coupled to the first variable delay generating unit and to the second variable delay generating unit, for zero-checking the normalized timing offset τ 1 (n), such that, for providing shifting and timing information for a first digital rate converter having a first conversion ratio ρ: the first digital rate converter is initialized to a normalized timing offset of τ init ; the second digital rate converter is initialized to a normalized timing offset of (1-ρτ init )modulo 1; and where zero-crossing occurs, the zero-crossing checking and resetting unit resets a second normalized timing offset τ 2 (k) to one of: substantially 1-ρτ 1 (n) where τ 1 (n) is close to zero (crossing from one-side); and substantially ρ[1-τ 1 (n)] where a normalized timing offset τ 1 (n) is near one (crossing from zero side); such that timing differences between the first digital sequence samples and the second output digital sequence samples are substantially detected and variations in the timing differences are substantially reduced; and D) a receiver unit, operably coupled to the digital synchronization unit, for at least receiving {x 2 (k)}.

Claim 12

A modem for at least one of: transmitting and receiving information, such that at least first and second digital rate converters (DRCs) are at least partially synchronized, the first DRC having an input of at least some first digital sequence samples {x 1 (k)} sampled at a first sampling rate and the second DRC having an input of at least some second digital sequence samples {y 2 (n)} related to the first digital sequence samples and sampled at a second sampling rate different from the first sampling rate, comprising at least: A) an encoder/modulator unit, operably coupled to receive information, for at least providing encoded/modulated information; B) a transmission filter unit, operably coupled to the encoder/modulator unit, for at least filtering the encoded/modulated information to provide first digital sequence samples in a transmission form, {x 1 (k)}; C) a digital synchronization unit, operably coupled to the transmission filter unit, for providing output samples {x 2 (k)} at least partially synchronized with {x 1 (k)}, wherein: the first DRC comprises at least: a first buffer, operably coupled to receive the first digital sequence samples {x 1 (k)}, for delaying and temporarily storing the first digital sequence samples {x 1 (k)}; a first digital resampler having at least a first delay unit, operably coupled to the first buffer, for shifting the first digital sequence samples into the first delay unit and for generating first output sequence samples {y 1 (n)} at substantially the second sampling rate utilizing a first selected sample timing in accordance with a first shift control signal m 1 (n) and a first desired normalized timing τ 1 (n); and a first variable delay generating unit having a normalized timing offset input Δτ 1 (n), Δτ 1 (n) being a first sampling time advance, and being operably coupled to the first digital resampler, for providing the first desired normalized timing offset τ 1 (n) and for providing the first shift control signal m 1 (n) determined from a previous normalized timing offset τ 1 (n-1); and the second DRC comprises at least: a second buffer, operably coupled to receive the second digital sequence samples {y 2 (n)} related to the first digital sequence samples {x 1 (k)}, for at least delaying and temporarily storing the second digital sequence samples {y 2 (n)} and providing the delayed, temporarily stored samples to a second digital resampler; a second digital resampler having at least a second delay unit, operably coupled to the second buffer and to a second variable delay generating unit, for shifting the second digital sequence samples into the second delay unit and for generating second output digital sequence samples {x 2 (n)} at substantially the first sampling rate utilizing a selected sample timing in accordance with a second desirable normalized timing offset τ 2 (k), and a second shifting control signal m 2 (n) from the second variable delay generating unit, the second variable delay generating unit having a normalized timing input Δτ 2 (k), Δτ 2 (k) being a second sampling time advance, and being operably coupled to the second digital resampler, for providing the second desired normalized timing offset τ 2 (k) and for providing the second shift control signal m 2 (n) determined from a previous normalized timing offset τ 2 (n-1), the second variable delay generating unit being operably coupled at least to the second digital resampler, for providing shift and timing information in accordance with a second sampling time advance Δτ 2 (k), adjustment to the second variable delay generating unit further being provided by at least one of the following: a) one of: the second buffer being further operably coupled to the second variable delay generating unit for providing a first feedback signal for queue-depth monitoring; and an output buffer of the second DRC being operably coupled to the second variable delay generating unit for providing a second feedback signal for queue-depth monitoring; such that the second variable delay generating unit provides shifting and timing information utilizing at least queue-depth monitoring for monitoring a depth of at least one of: an output buffer of the second output digital sequence samples {x 2 (k)}, and an input buffer of the second digital sequence samples {y 2 (n)}; and b) at least a zero-crossing checking and resetting unit, operably coupled to the first variable delay generating unit and to the second variable delay generating unit, for zero-checking the normalized timing offset τ 1 (n), such that, for providing shifting and timing information for a first digital rate converter having a first conversion ratio ρ: the first digital rate converter is initialized to a normalized timing offset of τ init ; the second digital rate converter is initialized to a normalized timing offset of (1-ρτ init )modulo 1; and where zero-crossing occurs, the zero-crossing checking and resetting unit resets a second normalized timing offset τ 2 (k) to one of: substantially 1-ρτ 1 (n) where τ 1 (n) is close to zero (crossing from one-side); and substantially ρ[1-τ 1 (n)] where a normalized timing offset τ 1 (n) is near one (crossing from zero side); such that timing differences between the first digital sequence samples and the second output digital sequence samples are substantially detected and variations in the timing differences are substantially reduced; and D) a receiver unit, operably coupled to the digital synchronization unit, for at least receiving {x 2 (k)}.

Claim 13

The modem of claim 10, further including: A) an echo canceller unit, operably coupled to the encoder/modulator unit, for at least providing an echo cancelling output; and B) a combiner, operably coupled to the echo canceller unit and to the digital synchronization unit, for substantially adding the echo cancelling output to an output of the digital synchronization unit, such that a substantially echo corrected input is provided to the receiver unit.

Claim 14

The modem of claim 10, wherein one of: Δτ 2 (k) is substantially equal to ρ, where ρ is a nominal rate-conversion ratio; and Δτ 2 (k) is substantially equal to ρ 2 Δτ 1 (n), where ρ is a nominal rate-conversion ratio.

Claim 15

The modem of claim 10, wherein the first sampling time advance Δτ 1 (n) is preselected by an external controller.

Claim 16

The modem of claim 10, wherein the first sampling time advance Δτ 1 (n) is determined from a nominal conversion ratio ρ such that Δτ 1 (n)=1/τ.

Claim 17

The modem of claim 10, wherein the first digital resampler further comprises at least a sample shifting unit for providing delayed first digital sequence samples having a first selected rate, a first predetermined number of subfilters, and a linear interpolator for selecting a second predetermined number of subfilter outputs for generating a desired sample.

Claim 18

The modem of claim 10, wherein the second variable delay generating unit provides shifting and timing information utilizing at least queue-depth monitoring for monitoring a depth of at least one of: an output buffer of the second output digital sequence samples {x 2 (k)} and an input buffer of the second digital sequence samples {y 2 (n)}.

Claim 19

The modem of claim 10, wherein, for a desired queue-depth D and a selected buffer being one of: the input buffer of {y 2 (n)} and the output buffer of x 2 (k), where the second variable delay generating unit further provides for: A) where the queue depth of the selected output buffer is greater than D, generating the second output digital sequence samples {x 2 (k)} at a rate smaller than the first sampling rate; B) where the queue depth of the selected output buffer is less than D, generating the second output digital sequence samples {x 2 (k)} at a rate greater than the first sampling rate; C) where the queue depth of the selected input buffer is greater than D, generating the second output digital sequence samples {x 2 (k)} at a rate greater than the first sampling rate; and D) where the queue depth of the selected input buffer is less than D, generating the second output digital sequence samples {x 2 (k)} at a rate smaller than the first sampling rate.

Claim 22

The method of claim 18, wherein Δτ 2 (k) is substantially equal to ρ, where ρ is a nominal rate-conversion ratio.

Claim 23

The method of claim 18, wherein Δτ 2 (k) is substantially equal to ρ 2 Δτ 1 (n), where τ is a nominal rate-conversion ratio.

Claim 24

The method of claim 18, wherein the first sampling time advance Δτ 1 (n) is preselected by an external controller.

Claim 25

The device of claim 18, wherein the first sampling time advance Δτ 1 (n) is determined from a nominal conversion ratio ρ such that Δτ 1 (n)=1/ρ.

Claim 26

The method of claim 18, further comprising the steps of providing delayed first digital sequence samples having a first selected rate, utilizing a first predetermined number of subfilters, and utilizing at least a linear interpolator for selecting a second predetermined number of subfilter outputs for generating a desired sample.

Claim 27

The method of claim 18, further including the step of queue-depth monitoring a depth of at least one of: an output buffer of the second output digital sequence samples x 2 (k) and an input buffer of the second digital sequence samples y 2 (n).

Claim 28

The method of claim 24, further including, for a desired queue-depth D and a selected buffer being one of: the input buffer of {y 2 (n)} and the output buffer of {x 2 (k)}, where the second variable delay generating unit further provides for: A) where the queue depth of the selected output buffer is greater than D, generating the second output digital sequence samples {x 2 (k)} at a rate smaller than the first sampling rate; B) where the queue depth of the selected output buffer is less than D, generating the second output digital sequence samples {x 2 (k)} at a rate greater than the first sampling rate; C) where the queue depth of the selected input buffer is greater than D, generating the second output digital sequence samples {x 2 (k)} at a rate greater than the first sampling rate; and D) where the queue depth of the selected input buffer is less than D, generating the second output digital sequence samples {x 2 (k)} at a rate smaller than the first sampling rate.

Claim 29

The method of claim 18, wherein the steps are utilized in a modem.

Claim 30

The method of claim 18, further including the step of zero-checking the normalized timing offset τ 1 (n), such that, for providing shifting and timing information for the first digital rate converter having a first conversion ratio ρ: the first digital rate converter is initialized to a normalized timing offset of τ init ; the second digital rate converter is initialized to a normalized timing offset of (1-ρτ init )modulo 1; and where zero-crossing occurs, resetting a second normalized timing offset τ 2 (k) to one of: substantially 1-ρτ 1 (n) where τ 1 (n) is close to zero (crossing from one-side); and substantially ρ[1-τ 1 (n)] where the normalized timing offset τ 1 (n) is near one (crossing from zero side).