Defective pixel compensation with memory using interpolation via plural sample-and-hold circuits

Abstract

Abstract A defect correction circuit for a solid-state imaging device, made up of a large number of charge-coupled devices, is disclosed. The correcting circuit includes a storage circuit for storing position data indicating the position of a defective pixel among a number of pixels of the solid-state imaging device, a sampling pulse generator for generating a first sampling pulse timed to the pixels of the imaging device, a second sampling pulse phase-shifted by 180° with respect to the first sampling pulse, a first sample-and-hold circuit for sample-holding an imaging output signal from the imaging device by the first sampling pulse, and a second sample-and-hold circuit for sample-holding an output signal of the first sample-and-hold circuit by the second sampling pulse. The sampling pulse generator withholds the outputting of a first sampling pulse associated with the defective pixel among the pixels of the solid-state imaging device, based on the position data read out from the storage device. The sampling pulse generator also elongates the pulse width of a second sampling pulse associated with the defective pixel as far as at least the trailing edge of a first sampling pulse succeeding the second sampling pulse. The defect correction circuit may additionally include a third sample-and-hold circuit for oversampling the imaging output signal corrected for defect by the second sample-and-hold circuit by a third sampling pulse to eliminate noise contained in the imaging output signal.

Inventors

• 👤 Masahiro Yamashita

Bibliographic Details