US5198707A
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US
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Integrated circuit with mode detection pin for tristate level detection
Assignee: STMicroelectronics SA
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Filing: 1991-05-24
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Granted: 1993-03-30
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Expires: 2011-05-24
Abstract
Abstract To enable a determined mode of operation, out of several possible modes, to be dictated from the exterior of an integrated circuit, there is provided a specific pin and a detector that is connected to the pin and is capable of detecting a logic level 0 or 1 or a high impedance state at this pin. The detector includes several switches and a resistor. It works in two successive phases and consumes no current at rest. A register memorizes the logic level of the pin during the two phases, and a decoder determines the state of the pin from the two memorized logic levels.
Inventors
- 👤 Jean Nicolai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:49
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31701
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
176 words
A CMOS integrated circuit, comprising: first and second power supply nodes; a first input pin; state detection circuitry, connected to said first input pin, comprising a single resistor, and a plurality of switches connected to said first input pin and to said resistor and to a register, and connected to be controlled by sequencing logic such that: in a first state of said switches, said resistor is connected between said input pin and said first power supply node, and said input pin is operatively connected to an input of said register; in a second state of said switches, said resistor is connected between said input pin and said second power supply node, and said input pin is operatively connected to an input of said register; and in a third state of said switches, said input of said register is connected to said second power supply node and not to the input pin; and wherein said sequencing logic also controls said register to selectably provide an output corresponding to values received during said first and second states.
Claim 2
Dependent Claim
176 words
A CMOS integrated circuit, comprising: first and second power supply nodes; a first input pin; state detection circuitry, connected to said first input pin, comprising a single resistor, and a plurality of switches connected to said first input pin and to said resistor and to a register, and connected to be controlled by sequencing logic such that: in a first state of said switches, said resistor is connected between said input pin and said first power supply node, and said input pin is operatively connected to an input of said register; in a second state of said switches, said resistor is connected between said input pin and said second power supply node, and said input pin is operatively connected to an input of said register; and in a third state of said switches, said input of said register is connected to said second power supply node and not to the input pin; and wherein said sequencing logic also controls said register to selectably provide an output corresponding to values received during said first and second states.
Claim 3
Dependent Claim
18 words
The integrated circuit of claim 1, wherein said resistor has a value of the order of 12 KΩ.
Claim 4
Dependent Claim
13 words
The integrated circuit of claim 1, wherein said register has a serial input.
Claim 5
Dependent Claim
37 words
The integrated circuit of claim 1, wherein said register provides a first output bit corresponding to the value received during said first state, and a second output bit corresponding to the value received during said second state.
Claim 6
Dependent Claim
61 words
The integrated circuit of claim 1, wherein said register provides a first output bit corresponding to the value received during said first state, and a second output bit corresponding to the value received during said second state; and further comprising decoding logic, connected to receive said two output bits of said register, and to drive one of three output lines accordingly.
Claim 7
Independent Claim
151 words
A method for discriminating among three states of an integrated circuit input pin, using a single resistor, comprising the steps of: (a) when it is desired to determine the state of the pin, then (a)(1) connecting the resistor between the pin and a power supply voltage, and simultaneously connecting the pin to an input of a buffer, and registering an output of said buffer to provide a first bit; and (a)(2) connecting the resistor between the pin and ground, and simultaneously connecting the pin to the input of said buffer, and registering the output of said buffer to provide a second bit; and (a)(3) decoding said first and second bits to determine the state of the pin; and (b) at all other times, not connecting the resistor between the pin and ground nor between the pin and the power supply voltage, and disconnecting the pin from the input of said buffer.
Claim 8
Independent Claim
151 words
A method for discriminating among three states of an integrated circuit input pin, using a single resistor, comprising the steps of: (a) when it is desired to determine the state of the pin, then (a)(1) connecting the resistor between the pin and a power supply voltage, and simultaneously connecting the pin to an input of a buffer, and registering an output of said buffer to provide a first bit; and (a)(2) connecting the resistor between the pin and ground, and simultaneously connecting the pin to the input of said buffer, and registering the output of said buffer to provide a second bit; and (a)(3) decoding said first and second bits to determine the state of the pin; and (b) at all other times, not connecting the resistor between the pin and ground nor between the pin and the power supply voltage, and disconnecting the pin from the input of said buffer.
Claim 9
Dependent Claim
14 words
The method of claim 6, wherein said step (a)(1) is performed before step (a)(2).
Claim 10
Dependent Claim
17 words
The method of claim 6, wherein said resistor has a value of the order of 12 KΩ.
Claim 11
Independent Claim
104 words
A method for discriminating among three states of an integrated circuit input pin, using a single resistor, comprising the steps of: (1) connecting the resistor between the pin and a power supply voltage, and simultaneously connecting the pin to an input of a buffer, and registering an output of said buffer to provide a first bit; and (2) connecting the resistor between the pin and ground, and simultaneously connecting the pin to the input of said buffer, and registering the output of said buffer to provide a second bit; and (3) decoding said first and second bits to determine the state of the pin.
Claim 12
Independent Claim
104 words
A method for discriminating among three states of an integrated circuit input pin, using a single resistor, comprising the steps of: (1) connecting the resistor between the pin and a power supply voltage, and simultaneously connecting the pin to an input of a buffer, and registering an output of said buffer to provide a first bit; and (2) connecting the resistor between the pin and ground, and simultaneously connecting the pin to the input of said buffer, and registering the output of said buffer to provide a second bit; and (3) decoding said first and second bits to determine the state of the pin.
Claim 13
Dependent Claim
15 words
The method of claim 9, wherein said step (1) is performed before said step (2).
Claim 14
Dependent Claim
17 words
The method of claim 9, wherein said resistor has a value of the order of 12 KΩ.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-29 | 1996-09-28 | 1997-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-29 | 2000-09-28 | 2001-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-29 | 2004-09-28 | 2005-03-30 | $7700.00 | Window Closed / Lapsed |