Memory arbitration between timekeeping circuitry and general purpose computer

Claim 3

The method of claim 1, wherein said step d) is delayed, if said steps a) or b) are occurring at the time that said step d) would normally occur, until step b) has been completed.

Claim 4

The method of claim 1, wherein said step b) occurs immediately after said step a).

Claim 5

Arbitration circuitry for arbitrating data being written into a common memory from a general-purpose computer system and a timekeeping system in which said timekeeping system performs memory access cycles, each of said memory access cycles comprising at least one write operation which writes a value corresponding to the current time, said memory access cycles being separated by periods of non access to said common memory by said timekeeping system, said arbitration circuitry comprising: a) first write means for writing data corresponding to a correction of said current time value from said general-purpose system into a first memory section of said common memory upon receipt of a write command signal from said general-purpose system; b) first transfer means for transferring data from said first memory section to a second memory section of said common memory after data is written into said first memory section by said general-purpose system; c) second write means for writing data corresponding to an increment of said current time value from said timekeeping system into said second memory section upon receipt of a write command signal from said timekeeping system if said general-purpose system has not written data into said first memory location during the present memory access cycle; and d) second transfer means for transferring data to said first memory section after data has been written into said second memory section by said timekeeping system.

Claim 6

Arbitration circuitry for arbitrating data being written into a common memory from a general-purpose computer system and a timekeeping system in which said timekeeping system performs memory access cycles, each of said memory access cycles comprising at least one write operation which writes a value corresponding to the current time, said memory access cycles being separated by periods of non access to said common memory by said timekeeping system, said arbitration circuitry comprising: a) first write means for writing data corresponding to a correction of said current time value from said general-purpose system into a first memory section of said common memory upon receipt of a write command signal from said general-purpose system; b) first transfer means for transferring data from said first memory section to a second memory section of said common memory after data is written into said first memory section by said general-purpose system; c) second write means for writing data corresponding to an increment of said current time value from said timekeeping system into said second memory section upon receipt of a write command signal from said timekeeping system if said general-purpose system has not written data into said first memory location during the present memory access cycle; and d) second transfer means for transferring data to said first memory section after data has been written into said second memory section by said timekeeping system.

Claim 7

Arbitration circuitry as set forth in claim 4 wherein the second transfer means further includes means for delaying the transfer from said second memory section to said first memory location if the first write means is writing data into said first memory section at the time that the second transfer means would normally transfer data or if said first transfer means is transferring data at the same time that said second transfer means would normally transfer data, said delay extending until after data is transferred from said first memory section to said second memory section.

Claim 8

The method of claim 1, wherein, in said step of periodically performing memory access cycles from said timekeeping system, each said write operation writes a value corresponding to the current time in seconds.

Claim 9

The method of claim 1, wherein, in said step of periodically performing memory access cycles from said timekeeping system, each said write operation writes a value corresponding to the current time in minutes and seconds.

Claim 10

The method of claim 1, wherein, in said step of periodically performing memory access cycles from said timekeeping system, each said write operation writes a value corresponding to the current time and data information.

Claim 11

The circuitry of claim 4, wherein said current time value includes a field corresponding to the current time in seconds.

Claim 12

The circuitry of claim 4, wherein said current time value includes a field corresponding to the current time in minutes and seconds.

Claim 13

The circuitry of claim 4, wherein said current time value includes a data value.

Claim 14

A computer system, comprising: a timekeeping circuit; a computer bus; a memory, comprising user and timekeeping memory sections having corresponding data structures, said timekeeping section being read-write accessible by said timekeeping circuit, and said user section being read-write accessible through said computer bus, independently of any access which may be made to said timekeeping section; and arbitration logic, configured and connected to: 1) when data is written in to said timekeeping section of said memory from said timekeeping circuit, 1.a) to immediately transfer the newly written data from said timekeeping section to said user section, unless said transfer operation is delayed or inhibited as specified below; and 2) when data is written into said user section of said memory from said bus: 2.a) to immediately transfer the newly written data from said user section to said timekeeping section; 2.b) to temporarily inhibit further writes into said timekeeping section, for the timekeeping-section byte corresponding to the user-section byte written into by the user and for all higher order timekeeping-section bytes but not for any lower order timekeeping-section bytes; and 2c) to delay any transfer of data from said timekeeping section to said user section while any write operation from said bus into said user section is occurring or any transfer from said user section to said timekeeping section is occurring.

Claim 15

A computer system, comprising: a timekeeping circuit; a computer bus; a memory, comprising user and timekeeping memory sections having corresponding data structures, said timekeeping section being read-write accessible by said timekeeping circuit, and said user section being read-write accessible through said computer bus, independently of any access which may be made to said timekeeping section; and arbitration logic, configured and connected to: 1) when data is written in to said timekeeping section of said memory from said timekeeping circuit, 1.a) to immediately transfer the newly written data from said timekeeping section to said user section, unless said transfer operation is delayed or inhibited as specified below; and 2) when data is written into said user section of said memory from said bus: 2.a) to immediately transfer the newly written data from said user section to said timekeeping section; 2.b) to temporarily inhibit further writes into said timekeeping section, for the timekeeping-section byte corresponding to the user-section byte written into by the user and for all higher order timekeeping-section bytes but not for any lower order timekeeping-section bytes; and 2c) to delay any transfer of data from said timekeeping section to said user section while any write operation from said bus into said user section is occurring or any transfer from said user section to said timekeeping section is occurring.

Claim 16

The system of claim 12, wherein said timekeeping circuit performs regular update cycles to update the information in said memory.

Claim 17

The system of claim 12, wherein said timekeeping circuit performs regular update cycles to update the information in said memory, sand said update cycles each include one or more accesses to said timekeeping section of said memory, and said update cycles are separated by periods which said timekeeping circuit does not access said memory.

Claim 18

The system of claim 12, wherein said timekeeping circuit performs regular update cycles, at an average frequency of precisely 1 Hz, to update the information in said memory.

Claim 19

The system of claim 12, wherein said timekeeping circuit performs regular update cycles, in each of which said timekeeping circuit reads information from said memory, computes a new value based on the information thus read, and writes said new value back into said timekeeping section of said memory.

Claim 20

The system of claim 12, wherein said timekeeping circuit performs regular update cycles to update the information in said memory, and wherein each said inhibition operation 2.b) performed by said arbitration circuit lasts until the end of the current update cycle of said timekeeping circuit.

Claim 21

The system of claim 12, wherein each said transfer operation 1a) is a block transfer.

Claim 22

The system of claim 12, wherein each said delay operation 2.c) performed by said arbitration circuit lasts until the completion of data transfer from said user section into said timekeeping section.

Claim 23

The system of claim 12, wherein said writes into said user section of said memory through said bus are performed by a general-purpose computer.

Claim 24

The system of claim 12, wherein said user section of said memory and said timekeeping section of said memory each include a field corresponding to the current time in seconds.

Claim 25

The system of claim 12, wherein said user section of said memory and said timekeeping section of said memory each include a field corresponding to the current time in minutes.

Claim 26

The system of claim 12, wherein said user section of said memory and said timekeeping section of said memory each include a field corresponding to the current date.

Claim 27

The system of claim 12, wherein said user section of said memory and said timekeeping section of said memory each include a field corresponding to the current year date.

Claim 28

A computer system, comprising: a timekeeping circuit; a computer bus; a memory, comprising user and timekeeping memory sections having corresponding data structures, said timekeeping section being read-write accessible by said timekeeping circuit, and said user section being read-write accessible through said computer bus, independently of any access which may be made to said timekeeping section; and arbitration logic, configured and connected to: 1) whenever data is written into said timekeeping section of said memory from said timekeeping circuit: 1.a) to transfer the newly written data from said timekeeping section to said user section, unless said transfer operation is delayed or inhibited as specified below; 2) and, whenever data is written into said user section of said memory from said bus: 2a) to transfer the newly written data from said user section to said timekeeping section; 2b) to temporarily inhibit further writes into said timekeeping section; and 2c) to delay any transfer of data from said timekeeping section to said user section while any write operation from said bus into said user section is occurring or any transfer from said user section to said timekeeping section is occurring.

Claim 29

A computer system, comprising: a timekeeping circuit; a computer bus; a memory, comprising user and timekeeping memory sections having corresponding data structures, said timekeeping section being read-write accessible by said timekeeping circuit, and said user section being read-write accessible through said computer bus, independently of any access which may be made to said timekeeping section; and arbitration logic, configured and connected to: 1) whenever data is written into said timekeeping section of said memory from said timekeeping circuit: 1.a) to transfer the newly written data from said timekeeping section to said user section, unless said transfer operation is delayed or inhibited as specified below; 2) and, whenever data is written into said user section of said memory from said bus: 2a) to transfer the newly written data from said user section to said timekeeping section; 2b) to temporarily inhibit further writes into said timekeeping section; and 2c) to delay any transfer of data from said timekeeping section to said user section while any write operation from said bus into said user section is occurring or any transfer from said user section to said timekeeping section is occurring.

Claim 30

The system of claim 25, wherein said timekeeping circuit performs regular update cycles to update the information in said memory.

Claim 31

The system of claim 25, wherein said timekeeping circuit performs regular update cycles to update the information in said memory, and said update cycles each include one or more accesses to said timekeeping section of said memory, and said update cycles are separated by periods during which said timekeeping circuit does not access said memory.

Claim 32

The system of claim 25, wherein said timekeeping circuit performs regular update cycles, at an average frequency of precisely 1 Hz, to update the information in said memory.

Claim 33

The system of claim 25, wherein said timekeeping circuit performs regular update cycles, in each of which said timekeeping circuit reads information from said memory, computes a new value based on the information thus read and writes said new value back into said timekeeping section of said memory.

Claim 34

The system of claim 25, wherein said timekeeping circuit performs regular update cycles to update the information in said memory, and wherein each said inhibition operation 2.b) performed by said arbitration circuit lasts until the end of the current update cycle of said timekeeping circuit.

Claim 35

The system of claim 25, wherein each said transfer operation 1a) is a block transfer.

Claim 36

The system of claim 25, wherein each said delay operation 2c) performed by said arbitration circuit lasts until the completion of data transfer from said user section into said timekeeping section.

Claim 37

The system of claim 25, wherein said writes into said user section of said memory through said bus are performed by a general-purpose computer.

Claim 38

The system of claim 25, wherein said user section of said memory and said timekeeping section of said memory each include a field corresponding to the current time in seconds.

Claim 39

The system of claim 25, wherein said user section of said memory and said timekeeping section of said memory each include a field corresponding to the current time in minutes.

Claim 40

The system of claim 25, wherein said user section of said memory and said timekeeping section of said memory each include a field corresponding to the current date.

Claim 41

The system of claim 25, wherein said user section of memory and said timekeeping section of said memory each include a field correponding to the current year date.