US5196805A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Distributed differential amplifier arrangement
Assignee: Voice Signals LLC
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Filing: 1992-01-31
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Granted: 1993-03-23
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Expires: 2012-01-31
Abstract
Abstract A N-stage differential distributed amplifier arrangement. The differential distributed amplifier arrangement includes a parallel connection of N-differential amplifiers. The inputs to the amplifiers are delayed so that the same input is received by each amplifier in sequence at a slightly later time than the preceding amplifier. The outputs of each amplifier are also delayed so that the output of the previous amplifier is added to the output of the next sequential amplifier. Thereby the output is an amplified version of the input. By appropriate grounding of inputs or outputs the differential distributed amplifier arrangement may convert from balanced signals to single-ended signals, from single-ended signals to balanced signals or from two inputs to two outputs.
Inventors
- 👤 William B. Beckwith
- 👤 Warren L. Seely
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 12:28
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/60; H03F3/605; H03F3/607
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
381 words
A differential distributed amplifier arrangement including at least one amplifier stage, said differential distributed amplifier arrangement comprising: input means adapted to receive at least one input signal for amplification; output means coupled to said input means, said output adapted to provide at least one output signal which is an amplified signal of said at least one input signal; said at least one amplifier stage including: amplifier means coupled to said input means said amplifier means producing said amplified signal; and means for transmitting said amplified signal to said output means, said means for transmitting coupled between said amplifier means and said output means; and said output means provides said at least one output signal in response to said amplified signal; said at least one amplifier stage includes a plurality of amplifier stages including a previous amplifier stage and a next amplifier stage, said previous and next amplifier stages coupled in parallel, said each amplifier stage coupled to said input means and to said output means; each of said plurality of amplifier stages includes said amplifier means and said means for transmitting; said means for transmitting including means for adding coupled to said amplifier means, said means for adding said amplified signal of said previous amplifier stage with said amplified signal of said next amplifier stage; each of said amplifier means includes: first and second voltage sources; first and second transistor means, each coupled to said first voltage source, each of said first and second transistor means providing for an output; third and fourth transistor means coupled respectively to said first and second transistor means and coupled in common, said third and fourth transistor means each providing for an input; and fifth transistor means coupled to the common connection of said third and fourth transistor means and to said second voltage source; and wherein said means for transmitting includes a plurality of serially connected inductor means, said means for adding being coupled between each of said plurality of inductor means; and said serial connection of inductor means connected to resistive means, said resistive means connected between one of said inductor means and a source of electrical ground; and wherein each of said transistor means includes field effect transistor means; and wherein said field effect transistor means each include high electron mobility transistors.
Claim 2
Dependent Claim
381 words
A differential distributed amplifier arrangement including at least one amplifier stage, said differential distributed amplifier arrangement comprising: input means adapted to receive at least one input signal for amplification; output means coupled to said input means, said output adapted to provide at least one output signal which is an amplified signal of said at least one input signal; said at least one amplifier stage including: amplifier means coupled to said input means said amplifier means producing said amplified signal; and means for transmitting said amplified signal to said output means, said means for transmitting coupled between said amplifier means and said output means; and said output means provides said at least one output signal in response to said amplified signal; said at least one amplifier stage includes a plurality of amplifier stages including a previous amplifier stage and a next amplifier stage, said previous and next amplifier stages coupled in parallel, said each amplifier stage coupled to said input means and to said output means; each of said plurality of amplifier stages includes said amplifier means and said means for transmitting; said means for transmitting including means for adding coupled to said amplifier means, said means for adding said amplified signal of said previous amplifier stage with said amplified signal of said next amplifier stage; each of said amplifier means includes: first and second voltage sources; first and second transistor means, each coupled to said first voltage source, each of said first and second transistor means providing for an output; third and fourth transistor means coupled respectively to said first and second transistor means and coupled in common, said third and fourth transistor means each providing for an input; and fifth transistor means coupled to the common connection of said third and fourth transistor means and to said second voltage source; and wherein said means for transmitting includes a plurality of serially connected inductor means, said means for adding being coupled between each of said plurality of inductor means; and said serial connection of inductor means connected to resistive means, said resistive means connected between one of said inductor means and a source of electrical ground; and wherein each of said transistor means includes field effect transistor means; and wherein said field effect transistor means each include high electron mobility transistors.
Claim 3
Dependent Claim
51 words
A differential distributed amplifier arrangement as claimed in claim 1, wherein: said amplifier means includes a plurality of inputs; and said input means including a plurality of serially connected inductor means, said inputs of said amplifier means each being connected between corresponding ones of said plurality of serially connected inductor means.
Claim 4
Dependent Claim
33 words
A differential distributed amplifier arrangement as claimed in claim 2, wherein said input means further includes resistor means connected between one of said serially connected inductor means and a source of electrical ground.
Claim 5
Dependent Claim
38 words
A differential distributed amplifier arrangement as claimed in claim 1, wherein said at least one amplifier stage includes a plurality of amplifier stages in the range of from 1 to N amplifier stages, wherein N is an integer.
Claim 6
Dependent Claim
25 words
A differential distributed amplifier arrangement as claimed in claim 1, wherein each of said field effect transistor means includes metal semiconductor field effect transistors (MESFETs).
Claim 7
Dependent Claim
22 words
A differential distributed amplifier arrangement as claimed in claim 1, wherein said field effect transistor means each include heterostructure bipolar transistor (HBTs).
Claim 8
Dependent Claim
25 words
A differential distributed amplifier arrangement as claimed in claim 6, wherein each of said first and second transistor means includes field effect transistor (FET) means.
Claim 9
Dependent Claim
25 words
A differential distributed amplifier arrangement as claimed in claim 6, wherein each of said field effect transistor means includes metal semiconductor field effect transistors (MESFETs).
Claim 10
Dependent Claim
66 words
A differential distributed amplifier arrangement as claimed in claim 1, wherein: said input means receiving first and second input signals, said first signal being an electrical ground signal, said second signal being a single-ended input signal; and said output means providing first and second output signals, said first and second output signals being of substantially equal magnitude and substantially opposite in phase forming a balanced output.
Claim 11
Dependent Claim
57 words
A differential distributed amplifier arrangement as claimed in claim 1, wherein: said input means receiving first and second input signals equal in amplitude and 180° out-of-phase; and said output means providing first and second output signals, said first output signal being connected to a source of electrical ground, said second output signal being a single-ended output signal.
Claim 12
Dependent Claim
41 words
A differential distributed amplifier arrangement as claimed in claim 1, wherein: said input means receives first and second input signals; and said output means provides first and second output signals which are amplified versions of said first and second input signals.
Claim 13
Dependent Claim
23 words
A differential distributed amplifier arrangement as claimed in claim 1, wherein said differential distributed amplifier arrangement comprises a microwave monolithic integrated circuit arrangement.
Claim 14
Dependent Claim
331 words
A differential distributed amplifier arrangement including at least one amplifier stage, said differential distributed amplifier arrangement comprising: input means adapted to receive at least one input signal for amplification; output means coupled to said input means, said output adapted to provide at least one output signal which is an amplified signal of said at least one input signal; said at least one amplifier stage including: amplified means coupled to said input means said amplifier means producing said amplified signal; and means for transmitting said amplified signal to said output means, said means for transmitting coupled between said amplifier means and said output means; and said output means provides said at least one output signal in response to said amplified signal; said at least one amplifier stage includes a plurality of amplifier stages including a previous amplifier stage and a next amplifier stage, said previous and next amplifier stages coupled in parallel, said each amplifier stage coupled to said input means and to said output means; each of said plurality of amplifier stages includes said amplifier means and said means for transmitting; said means for transmitting including means for adding coupled to said amplifier means, said means for adding said amplified signal of said previous amplifier stage with said amplified signal of said next amplifier stage; each of said amplifier means includes: first and second voltage sources; first and second resistor means having a common connection with said first voltage source; first and second inductor means coupled respectively to said first and second resistor means; first and second transistor means coupled respectively to said first and second inductor means, said common connection of said first and second transistor means and said first and second inductor means each providing an output, said first and second transistor means further coupled together in common, said first and second transistor means each providing an input; and third inductor means coupled between the common connection of said first and second transistor means and said second voltage source.
Claim 15
Dependent Claim
331 words
A differential distributed amplifier arrangement including at least one amplifier stage, said differential distributed amplifier arrangement comprising: input means adapted to receive at least one input signal for amplification; output means coupled to said input means, said output adapted to provide at least one output signal which is an amplified signal of said at least one input signal; said at least one amplifier stage including: amplified means coupled to said input means said amplifier means producing said amplified signal; and means for transmitting said amplified signal to said output means, said means for transmitting coupled between said amplifier means and said output means; and said output means provides said at least one output signal in response to said amplified signal; said at least one amplifier stage includes a plurality of amplifier stages including a previous amplifier stage and a next amplifier stage, said previous and next amplifier stages coupled in parallel, said each amplifier stage coupled to said input means and to said output means; each of said plurality of amplifier stages includes said amplifier means and said means for transmitting; said means for transmitting including means for adding coupled to said amplifier means, said means for adding said amplified signal of said previous amplifier stage with said amplified signal of said next amplifier stage; each of said amplifier means includes: first and second voltage sources; first and second resistor means having a common connection with said first voltage source; first and second inductor means coupled respectively to said first and second resistor means; first and second transistor means coupled respectively to said first and second inductor means, said common connection of said first and second transistor means and said first and second inductor means each providing an output, said first and second transistor means further coupled together in common, said first and second transistor means each providing an input; and third inductor means coupled between the common connection of said first and second transistor means and said second voltage source.
Claim 16
Dependent Claim
23 words
A differential distributed amplifier arrangement as claimed in claim 12, wherein said differential distributed amplifier arrangement comprises a microwave monolithic integrated circuit arrangement.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-22 | 1996-09-21 | 1997-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-22 | 2000-09-21 | 2001-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-22 | 2004-09-21 | 2005-03-23 | $7700.00 | Window Closed / Lapsed |