Integrated D/A converter including means for reducing glitches

Claim 2

An integrated digital-to-analogue (D/A) converter circuit provided with a device for reducing glitches, which converts control signals having n binary states Bn into analogue signals and which comprises, n differential pairs Pn of transistors T1n and T2n connected to n current generators which supply currents of a value In weighted according to the binary weights 2 n of the binary states Bn, characterized in that, the transistors T1n receive their respective binary control signals and the transistors T2n receive respective binary control signals which are inverse to the control signals for the transistors T1n, the instant of triggering of the differential pairs at the leading edge of the control signal is shifted over the instants of triggering at a trailing edge of the control signal in that the shift of the triggering threshold of the transistors T1n with respect to the transistors T2n is effected over a constant value Vd obtained by the device for reducing glitches and comprising respective resistors connected in series with the emitters of the transistors of one of the series of transistors T1n or T2n in such a manner that Rn.In/2=Vd.

Claim 3

An integrated digital-to-analogue (D/A) converter circuit according to claim 1, characterized in that the integrated circuit is made in fast bipolar isolation diffusion technique and the vlaue of Vd is substantially between 10 mV and 70 mV.

Claim 4

A D/A converter comprising: a plurality of n differential pairs of transistors T 1n , T 2n where n is the number of bits in a digital signal to be converted to an analog output signal, means for applying the n bits of digital signal to respective control electrodes of respective ones of the transistors T 1n and T 2n of the differential pairs so that the transistors t 1n , T 2n of each differential pair receive binary control signals that are inverse to one another whereby when T 1n is turned on T 2n is turned off, and vice versa, a plurality of n current generators which supply binary weighted currents I n , means connecting said current generators to emitters of respective ones of the transistors (either transistors T 1n or T 2n ) of respective differential pairs, means connecting collectors of the T 1n transistors in common to a first output line and collectors of the T 2n transistors in common to a second output line, and means for reducing glitches in the analog output signal comprising a plurality of n resistors R n connecting emitters of the other ones of said transistors to respective ones of said n current generators, where V d =R n I n /2 thereby to shift the trigger voltage threshold of the transistors T 1n with respect to the transistors T 2n over a constant voltage value V d .

Claim 5

A D/A converter comprising: a plurality of n differential pairs of transistors T 1n , T 2n where n is the number of bits in a digital signal to be converted to an analog output signal, means for applying the n bits of digital signal to respective control electrodes of respective ones of the transistors T 1n and T 2n of the differential pairs so that the transistors t 1n , T 2n of each differential pair receive binary control signals that are inverse to one another whereby when T 1n is turned on T 2n is turned off, and vice versa, a plurality of n current generators which supply binary weighted currents I n , means connecting said current generators to emitters of respective ones of the transistors (either transistors T 1n or T 2n ) of respective differential pairs, means connecting collectors of the T 1n transistors in common to a first output line and collectors of the T 2n transistors in common to a second output line, and means for reducing glitches in the analog output signal comprising a plurality of n resistors R n connecting emitters of the other ones of said transistors to respective ones of said n current generators, where V d =R n I n /2 thereby to shift the trigger voltage threshold of the transistors T 1n with respect to the transistors T 2n over a constant voltage value V d .

Claim 6

A D/A converter as claimed in claim 3 wherein said n resistors have resistance values R n distributed across said differential pairs in a binary weighted manner.

Claim 7

A D/A converter as claimed in claim 3 wherein V d is the voltage drop across respective ones of said n resistors.

Claim 8

A D/A converter as claimed in claim 3 wherein V d is in the range of 10 mV to 70 mV.