Data driver circuit of liquid crystal display for achieving digital gray-scale

Claim 2

A data line driver circuit providing a plurality of digitally selectable, gray-scale display drive signal outputs, of a first number, for a liquid crystal display, comprising: plural power source voltage terminals at a second number of respective and different, plural voltage levels, the second number being less than the first number; a driver circuit output terminal; a plurality of analog switches with corresponding load resistances, each having an input terminal connected to a corresponding one of the power source voltage terminals, an output terminal connected to the driver circuit output terminal and associated switching terminals for receiving corresponding input ON signals, each analog switch being selectively switched to an ON condition by a corresponding input ON signal; a source of display data signals defining the specific gray-scale value, of the first number of gray-scale values, of a display to be produced by the liquid crystal display; and a selection circuit having input terminals connected to the display data signal source for receiving the display data signals, having output terminals respectively connected to the associated switching terminals of the plurality of analog switches, and being responsive to the received display data signals for selectively generating at and transmitting from the output terminals thereof one or more input ON signals respectively to one or more of the associated input terminals of the plurality of analog switches in accordance with and in response to the specific gray-scale value defined by the received display data signals for the corresponding display to be produced, the analog switches which receive the ON signals from the selection circuit producing outputs through the corresponding load resistances thereof and thereby at the respective output terminals thereof, and which outputs are combined at the driver circuit output terminal as the thereby selected, gray-scale display drive signal output of the data line driver circuit.

Claim 3

A data line driver circuit as recited in claim 1, wherein: the plurality of analog switches is arranged in a plurality of groups, each group comprising plural analog switches; and the selection circuit selectively transmits one or a plurality of ON signals to the corresponding one or the corresponding plurality of the analog switches of each of the plurality of groups of analog switches.

Claim 4

A data line driver circuit as recited in claim 1, wherein: the plurality of analog switches is arranged in a plurality of groups, each group comprising plural analog switches; and the selection circuit selectively transmits one or a plurality of ON signals to the corresponding one or the corresponding plurality of the analog switches in each group of plural analog switches and wherein the respective input terminals of the corresponding plurality of analog switches of each group to which the ON signals are selectively transmitted are connected to corresponding power source voltage terminals having adjacent, different voltage level values.

Claim 5

A data line driver circuit as recited in claim 1, wherein: each analog switch comprises first and second transistors of respective, different conductivity types having corresponding first and second control terminals and being connected in parallel between the corresponding input and output terminals of the analog switch; and the voltage selection circuit has, for each analog switch, a respective pair of first and second output terminals corresponding to the first and second control terminals of the respective first and second transistors of the analog switch and supplies, as the ON signal, a selection signal and an inverted selection signal respectively to the first and second control terminals of the first and second transistors of the analog switch in accordance with the respective, different conductivity types thereof.

Claim 6

A data line driver circuit as recited in claim 1, wherein: the first and second transistors of each analog switch respectively comprise a P-channel MOSFET and N-channel MOSFET having respective gate terminals; and the respective control terminals of the first and second transistors comprise the respective gate terminals of the P-channel and N-channel MOSFETs.

Claim 7

A data line driver circuit as recited in claim 1, further comprising: a plurality of resistance elements respectively connected between the input terminals of the plurality of analog switches and the corresponding power source voltage terminals.

Claim 8

A data line driver circuit as recited in claim 6, wherein: the plurality of analog switches is arranged in a plurality of groups, each group comprising plural analog switches; and the selection circuit selectively transmits an ON signal to one or more of the plural analog switches in each of the plurality of groups of analog switches in accordance with and in response to the display data input signal.

Claim 9

A data line driver circuit as recited in claim 6, wherein: the plurality of analog switches are arranged in a plurality of groups, each group comprising plurality switches; and the selection circuit selectively transmits one or a plurality of ON signals to the corresponding one or the corresponding plurality of the analog switches in each group of plural analog switches and wherein the respective input terminals of the corresponding plurality of analog switches of each group to which ON signals are selectively transmitted are connected to corresponding power source voltage terminals having adjacent, different voltage level values.

Claim 10

A data line driver circuit as recited in claim 6, wherein: each analog switch comprises first and second parallel transistors of respective, different conductivity types and corresponding first and second control terminals and connected in parallel between the corresponding input and output terminals of the analog switch; and the voltage selection circuit has, for each analog switch, a respective pair of first and second output terminals corresponding to the first and second control terminals of the respective first and second transistors of the analog switch and supplies, as the ON signal, a selection signal and an inverted selection signal respectively to the first and second control terminals of the first and second transistors of the analog switch in accordance with the respective, different conductivity types thereof.

Claim 11

A data line driver circuit as recited in claim 6, wherein: the first and second transistors of each analog switch respectively comprise a P-channel MOSFET and N-channel MOSFET; and the respective control terminals of the first and second transistors comprise the respective gate terminals of the P-channel and N-channel MOSFETs.

Claim 12

A data line driver circuit as recited in claim 6, wherein: each analog switch, when switched to an ON-state by receipt of an ON-signal from the selection circuit, has a respective resistance value; and the resistance value of each of the plurality of resistance elements is higher than the resistance value of the load resistance in the ON state of the respectively associated analog switch.

Claim 13

A data line driver circuit as recited in claim 6, wherein: the driver circuit is implemented in a semiconductor substrate; and each of the plurality of series-connected resistance elements is formed in the semiconductor substrate in accordance with a selected one of diffusion resistance, ion implantation resistance, and thin film resistance formation methods.

Claim 14

A data line driver circuit providing a plurality of digitally selectable, gray-scale display drive signal outputs, of a first number, for a liquid crystal display, comprising: plural power source voltage terminals at a second number of respective and different, plural voltage levels, the second number being less than the first number; a driver circuit output terminal; a plurality of analog switch groups, each group comprising at least two analog switches having corresponding parallel load resistances and input terminals connected to corresponding ones of the power source voltage terminals, an output terminal connected to the driver circuit output terminal and associated switching terminals for receiving corresponding input ON signals, each analog switch being selectively switched to an ON condition by a corresponding input ON signal; a source of display data signals defining the specific gray-scale value, of the first number of gray-scale values, of a display to be produced by the liquid crystal display; and a selection circuit having input terminals connected to the display data signal source for receiving the display data signals, having output terminals respectively connected to the associated switching terminals of the plurality of analog switches, and being responsive to the received display data signals for selectively generating at and transmitting from the output terminals thereof at least one input ON signal to the associated input terminal of an analog switch of each analog switch group in accordance with and in response to the specific gray-scale value defined by the received display data signals for the corresponding display to be produced, the analog switches which receive the ON signals form the selection circuit producing outputs through the corresponding load resistances thereof and thereby at the respective output terminals thereof, and which outputs are combined at the driver circuit output terminal as the thereby selected, gray-scale display drive signal output of the data line driver circuit.

Claim 15

A data line driver circuit providing a plurality of digitally selectable, gray-scale display drive signal outputs, of a first number, for a liquid crystal display, comprising: plural power source voltage terminals at a second number of respective and different, plural voltage levels, the second number being less than the first number; a driver circuit output terminal; a plurality of analog switch groups, each group comprising at least two analog switches having corresponding parallel load resistances and input terminals connected to corresponding ones of the power source voltage terminals, an output terminal connected to the driver circuit output terminal and associated switching terminals for receiving corresponding input ON signals, each analog switch being selectively switched to an ON condition by a corresponding input ON signal; a source of display data signals defining the specific gray-scale value, of the first number of gray-scale values, of a display to be produced by the liquid crystal display; and a selection circuit having input terminals connected to the display data signal source for receiving the display data signals, having output terminals respectively connected to the associated switching terminals of the plurality of analog switches, and being responsive to the received display data signals for selectively generating at and transmitting from the output terminals thereof at least one input ON signal to the associated input terminal of an analog switch of each analog switch group in accordance with and in response to the specific gray-scale value defined by the received display data signals for the corresponding display to be produced, the analog switches which receive the ON signals form the selection circuit producing outputs through the corresponding load resistances thereof and thereby at the respective output terminals thereof, and which outputs are combined at the driver circuit output terminal as the thereby selected, gray-scale display drive signal output of the data line driver circuit.

Claim 16

A data line driver circuit as recited in claim 13 wherein the respective load resistances of the analog switches of each group of analog switches have corresponding, different load resistance values.

Claim 17

A data line driver circuit as recited in claim 14, wherein each group of analog switches comprises two analog switches and the corresponding load resistances thereof have a ratio of load resistance values of 1 to 2.

Claim 18

A data line driver circuit as recited in claim 13, wherein the selection circuit, in accordance with and in response to the specific gray-scale value defined by the received data display signals for the corresponding display to be produced, selectively generates and transmits a single input ON signal to the associated switching terminal of the specific analog switch which specific analog switch is connected at the input terminal thereof to the power source voltage terminal having the voltage level corresponding the specific gray-scale value defined by the received display data signal, or selectively and simultaneously generates and transmits at least first and second input ON signals to the associated input terminals of at least first and second analog switches respectively of different analog switch groups thereby to produce a display drive signal output having a voltage level which is intermediate the respective voltage levels of the respective power source voltage terminals connected to the input terminals of the at least first and second selected analog switches of the different analog switch groups, divided by the respective load resistances thereof.

Claim 19

A data line driver circuit as recited in claim 16, wherein the respective load resistances of the analog switches of each analog switch group have corresponding, different load resistance values.

Claim 20

A data line driver circuit as recited in claim 17, wherein each group of analog switches comprises two analog switches and the corresponding load resistances thereof have a ratio of load resistance values of 1 to 2.

Claim 21

A digital data driver circuit as recited in claim 16, wherein the selection circuit, in accordance with the received display data signals, simultaneously generates and transmits a corresponding number of input ON signals to a corresponding number of plural, associated input terminals of corresponding, plural analog switches of a given analog switch group thereby for varying the combined value of the corresponding load resistances and thus to vary the divided voltage level of the display drive signal output produced at the driver circuit output terminal.

Claim 22

A data line driver circuit as recited in claim 19, wherein the corresponding load resistances of the analog switches of each analog switch group have respective, different load resistance values.

Claim 23

A data line driver circuit as recited in claim 20, wherein each group of analog switches comprises two analog switches and the respective load resistances thereof have a ratio of load resistance value of 1 to 2.

Claim 24

A delay line driver circuit as recited in claim 13, further comprising: a plurality of resistance elements respectively connected between the input terminals of the plurality of analog switches and the corresponding power source voltage terminals.

Claim 25

A data line driver circuit as recited in claim 22, the respective load resistances of the analog switches of each group of analog switches have corresponding, different load resistance values.

Claim 26

A data line driver circuit as recited in claim 23, wherein each group of analog switches comprises two analog switches and the respective load resistances thereof have a ratio of load resistance values of 1 to 2.

Claim 27

A data line driver circuit as recited in claim 22, wherein the selection circuit, in accordance with and in response to the specific gray-scale value defined by the received data display signals for the corresponding display to be produced, selectively generates and transmits a single input ON signal to the associated switching terminal of the specific analog switch which specific analog switch is connected at the input terminal thereof to the power source voltage terminal having the voltage level corresponding the specific gray-scale value defined by the received display data signal, or selectively and simultaneously generates and transmits at least first and second input ON signals to the associated input terminals of at least first and second analog switches respectively of different analog switch groups thereby to produce a display drive signal output having a voltage level which is intermediate the respective voltage levels of the respective power source voltage terminals connected to the input terminals of the at least first and second selected analog switches of the different analog switch groups, divided by the respective load resistances thereof.

Claim 28

A data line driver circuit as recited in claim 25, wherein the respective load resistances of the analog switches of each group of analog switches have corresponding, different load resistance values.

Claim 29

A data line driver circuit as recited in claim 26, wherein each group of analog switches comprises two analog switches and the respective load resistances thereof have a ratio of load resistance values of 1 to 2.

Claim 30

A data line driver circuit as recited in claim 25, wherein the selection circuit, in accordance with the received display data signals, simultaneously generates and transmits a corresponding number of input ON signals to a corresponding number of plural, associated input terminals of corresponding, plural analog switches of a given analog switch group thereby for varying the combined value of the corresponding load resistances and thus to vary the divided voltage level of the display drive signal output produced at the driver circuit output terminal.

Claim 31

A data line driver circuit as recited in claim 28, wherein the respective load resistances of the analog switches of each analog switch group have corresponding, different load resistance values.

Claim 32

A data line driver circuit as recited in claim 29, wherein each group of analog switches comprises two analog switches and the respective load resistances thereof have a ratio of load resistance values of 1 to 2.

Claim 33

A data line driver circuit as recited in claim 13, each analog switch, when switched to an ON-state by receipt of an ON-signal from the selection circuit, has a respective resistance value; and the resistance value of each of the plurality of resistance elements is higher than the resistance value of the load resistance in the ON state of the respectively associated analog switch.

Claim 34

A data line driver circuit as recited in claim 13, wherein: the driver circuit is implemented in a semiconductor substrate; and each of the plurality of series-connected resistance elements is formed in the semiconductor substrate in accordance with a selected one of diffusion resistance, ion implantation resistance, and thin film resistance formation methods.