Method and apparatus for data encryption or decryption

Claim 2

A cryptographic apparatus comprising: linear feedback shift register means having a seed input for accepting a random number and having a weighting input for accepting tap weights; adder means coupled to said linear feedback shift register means, said adder means for combining output from designated cells of said linear feedback shift register means to form an output signal from said linear feedback shift register means comprising a psuedo-random code; control means coupled to said adder means, said control means for selecting said designated cells of said linear feedback shift register means; ciphering device means including a Data Encryption Standard ciphering device operating in Cipher Feedback Mode, said ciphering device means coupled to said linear feedback shift register means, said ciphering device means for encrypting the pseudo-random code; data input means, said data input means for accepting an input digital message; and data output means, said data output means for providing an output digital message; and combiner means, one input of said combiner means coupled to said ciphering device means, another input of said combiner means coupled to said data input means, and an output of said combiner means coupled to said data output means, said combiner means for combining signals from said data input means to signals from said ciphering device means to provide output signals to said data output means.

Claim 3

The cryptographic apparatus claimed in claim 1, wherein said combiner means comprises an adder circuit.

Claim 4

The cryptographic apparatus claimed in claim 1, wherein said Data Encryption Standard ciphering device operates in accordance with Decrypt Mode.

Claim 5

The cryptographic apparatus claimed in claim 1, wherein said Data Encryption Standard ciphering device operates in accordance with Encrypt Mode.

Claim 6

The cryptographic apparatus claimed in claim 1, wherein said linear feedback shift register means comprises an N-stage linear feedback shift register, wherein N represents a number of stages comprising said N-stage linear feedback shift register and N>25.

Claim 7

A cryptographic communications system comprising one or more combinations of: at least a first cryptographic communications terminal, comprising: a first linear feedback shift register which is externally programmable at arbitrary intervals to change a particular pseudo-random code generated thereby and having a seed input for accepting a random number and a weighting input for accepting tap weights; a first ciphering device, said first ciphering device coupled to said linear feedback shift register, said first ciphering device comprising a first Data Encryption Standard ciphering device operating in Cipher Feedback Mode; a data input; a first data output; and a first adder circuit, one input of said first adder circuit coupled to said first ciphering device, another input of said first adder circuit coupled to said data input, and an output of said first adder circuit coupled to said first data output; and at least a second cryptographic communications terminal comprising: a second linear feedback shift register which is externally programmable at arbitrary intervals coinciding with said arbitrary intervals at which said first linear feedback shift register is externally programmed to change a particular pseudo-random code generated thereby and having a seed input for accepting a random number and a weighting input for accepting tap weights, said first and second linear feedback shift registers operating to generate the same pseudo-random code; a second ciphering device, said second ciphering device coupled to said second linear feedback shift register, said second ciphering device comprising a second Data Encryption Standard ciphering device operating in Cipher Feedback Mode; a second data output; and a second adder circuit, one input of said second adder circuit coupled to said second ciphering device, another input of said second adder circuit coupled to said first data output, and an output of said second adder circuit coupled to said second data output.

Claim 8

A cryptographic communications system comprising one or more combinations of: at least a first cryptographic communications terminal, comprising: a first linear feedback shift register which is externally programmable at arbitrary intervals to change a particular pseudo-random code generated thereby and having a seed input for accepting a random number and a weighting input for accepting tap weights; a first ciphering device, said first ciphering device coupled to said linear feedback shift register, said first ciphering device comprising a first Data Encryption Standard ciphering device operating in Cipher Feedback Mode; a data input; a first data output; and a first adder circuit, one input of said first adder circuit coupled to said first ciphering device, another input of said first adder circuit coupled to said data input, and an output of said first adder circuit coupled to said first data output; and at least a second cryptographic communications terminal comprising: a second linear feedback shift register which is externally programmable at arbitrary intervals coinciding with said arbitrary intervals at which said first linear feedback shift register is externally programmed to change a particular pseudo-random code generated thereby and having a seed input for accepting a random number and a weighting input for accepting tap weights, said first and second linear feedback shift registers operating to generate the same pseudo-random code; a second ciphering device, said second ciphering device coupled to said second linear feedback shift register, said second ciphering device comprising a second Data Encryption Standard ciphering device operating in Cipher Feedback Mode; a second data output; and a second adder circuit, one input of said second adder circuit coupled to said second ciphering device, another input of said second adder circuit coupled to said first data output, and an output of said second adder circuit coupled to said second data output.

Claim 9

The cryptographic communications system claimed in claim 6, wherein one of said first or second cryptographic communications terminals operates to produce an encrypted message from a plain-text message and another of said first or second cryptographic communications terminals operates to produce a plain-text message from said encrypted message.

Claim 10

The cryptographic communications system claimed in claim 6, wherein said first and second adder circuits each comprise exclusive-OR means.

Claim 11

The cryptographic apparatus claimed in claim 6, wherein said first and second Data Encryption Standard ciphering devices operate in accordance with Encrypt Mode.

Claim 12

The cryptographic apparatus claimed in claim 6, wherein said first and second Data Encryption Standard ciphering devices operate in accordance with Decrypt Mode.

Claim 13

The cryptographic communications system claimed in claim 6, wherein said data input is a video data input, and said first and second data outputs are video data outputs.

Claim 14

The cryptographic communications system claimed in claim 6, wherein said data input is a facsimile signal input, and said first and second data outputs are facsimile signal outputs.

Claim 15

The cryptographic communications system claimed in claim 6, wherein said data input is a digitally encoded voice signal input, and said first and second data outputs are digitally encoded voice signal outputs.

Claim 18

The method for operation of a ciphering engine as claimed in claim 14, wherein said generating step further includes the step of using a Data Encryption Standard device in Decrypt Cipher Feedback Mode and operating on the pseudo-random bit stream from the programmable linear feedback shift register to generate a traffic key stream.

Claim 19

The method for operation of a ciphering engine claimed in claim 14, wherein said combining step further includes the step of performing a logical exclusive-OR operation to add the input data stream to the traffic key stream.

Claim 20

The method for operation of a ciphering engine claimed in claim 14, wherein the input data stream comprises a cipher-text data stream and wherein said combining step comprises the step of decrypting the cipher-text data stream to produce a plain-text output data stream.

Claim 21

The method for operation of a ciphering engine claimed in claim 14, wherein the input data stream comprises a plain-text stream and wherein said combining step comprises the step of encrypting the plain-text data stream to produce a cipher-text output data stream.

Claim 22

The method for operation of a ciphering engine claimed in claim 14, wherein said using step includes the step of using a programmable linear feedback shift register having N stages, where N is greater than twenty-five, to obtain a pseudo-random bit stream.