Patent US5195050A successfully refreshed from Google Patents.
US5195050A
Expired / Lapsed
US
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Single chip, mode switchable, matrix multiplier and convolver suitable for color image processing
Assignee: Eastman Kodak Co
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Filing: 1990-08-20
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Granted: 1993-03-16
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Expires: 2010-08-20
Abstract
Abstract An integrated circuit that uses the same coefficient registers, multipliers and adders to perform both matrix multiplication and convolution operations. The multipliers are arranged in columns and rows with the matrix multiplication adders located in the corresponding columns and with the adder for producing the convolution output located in one of the columns. A mode selection switch causes the multiplexers to change input data routing based on the mode selected. The circuit allows loading of all the coefficients or selection of hardwired coefficients. By rerouting the inputs of the multipliers using the multiplexers, the circuit can be easily configured for either mode of operation. The outputs corresponding to the columns are either output directly during matrix multiplication or provided to the convolution adder. The provision of an internal pseudo random number generator, serial inputs and outputs for test data and a signature analysis signal generating circuit allows the circuit to be easily internally tested.
Inventors
- 👤 Ken W. Hsu
- 👤 Lionel J. D'Luna
- 👤 Hur Jay Yeh
- 👤 Glen W. Brown
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:50
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/16
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
252 words
A circuit for selectable matrix multiplication and convolution operations and receiving parallel inputs at a data rate at data inputs and having a mode selection input, comprising: input routing means for routing the parallel inputs at the data rate responsive to selection of one of a matrix multiplication mode and a convolution mode, and said input routing means comprising: input buffer registers connected to the data inputs and to said operation means; first multiplexers connected to the data and mode selection inputs and to said input buffer registers; first storage buffer registers connected to said first multiplexers; second multiplexers connected to the data and mode selection inputs and to said first storage buffer registers; and second storage buffer register connected to said second multiplexers; operation means for performing, at the data rate, one of a matrix multiplication and a convolution operation using the routed inputs responsive to the selection and producing parallel outputs at the data rate during matrix multiplication and a convolution output at the data rate during convolution, said operation means comprising: coefficient register storing coefficient; first multipliers connected to said input buffer registers and said coefficient registers; second multipliers connected to said first storage buffer registers and said coefficient registers; third multipliers connected to said second storage buffer register and said coefficient registers; a first adder connected to said first multipliers; a second adder connected to said second multiplies; a third adder connected to said third multipliers; and a fourth adder connected to said first, second and third adders.
Claim 2
Dependent Claim
252 words
A circuit for selectable matrix multiplication and convolution operations and receiving parallel inputs at a data rate at data inputs and having a mode selection input, comprising: input routing means for routing the parallel inputs at the data rate responsive to selection of one of a matrix multiplication mode and a convolution mode, and said input routing means comprising: input buffer registers connected to the data inputs and to said operation means; first multiplexers connected to the data and mode selection inputs and to said input buffer registers; first storage buffer registers connected to said first multiplexers; second multiplexers connected to the data and mode selection inputs and to said first storage buffer registers; and second storage buffer register connected to said second multiplexers; operation means for performing, at the data rate, one of a matrix multiplication and a convolution operation using the routed inputs responsive to the selection and producing parallel outputs at the data rate during matrix multiplication and a convolution output at the data rate during convolution, said operation means comprising: coefficient register storing coefficient; first multipliers connected to said input buffer registers and said coefficient registers; second multipliers connected to said first storage buffer registers and said coefficient registers; third multipliers connected to said second storage buffer register and said coefficient registers; a first adder connected to said first multipliers; a second adder connected to said second multiplies; a third adder connected to said third multipliers; and a fourth adder connected to said first, second and third adders.
Claim 3
Dependent Claim
208 words
A circuit for selectable matrix multiplication and convolution receiving data over data inputs, and a mode selection over a mode input, said circuit comprising: first input registers connected to said data inputs; first coefficient registers; first multipliers connected to said first input and coefficient registers; first output registers connected to said first multipliers; first adders connected to said first output registers; first multiplexers connected to said data inputs, said first input registers and said mode selection input; second input registers connected to said first multiplexers; second coefficient registers; second multipliers connected to said second input and coefficient registers; second output registers connected to said second multipliers; second adders connected to said second output registers; second multiplexers connected to said data inputs, said second input registers and said mode selection input; third input registers connected to said second multiplexers; third coefficient registers; third multipliers connected to said third input and coefficient registers; third output registers connected to said third multipliers; third output registers connected to said third multipliers; third adders connected to said third output registers; buffer registers connected to said first, second and third adders; fourth adders connected to said buffer registers; and an output multiplexer connected to said second and fourth adders and to said mode input.
Claim 4
Dependent Claim
208 words
A circuit for selectable matrix multiplication and convolution receiving data over data inputs, and a mode selection over a mode input, said circuit comprising: first input registers connected to said data inputs; first coefficient registers; first multipliers connected to said first input and coefficient registers; first output registers connected to said first multipliers; first adders connected to said first output registers; first multiplexers connected to said data inputs, said first input registers and said mode selection input; second input registers connected to said first multiplexers; second coefficient registers; second multipliers connected to said second input and coefficient registers; second output registers connected to said second multipliers; second adders connected to said second output registers; second multiplexers connected to said data inputs, said second input registers and said mode selection input; third input registers connected to said second multiplexers; third coefficient registers; third multipliers connected to said third input and coefficient registers; third output registers connected to said third multipliers; third output registers connected to said third multipliers; third adders connected to said third output registers; buffer registers connected to said first, second and third adders; fourth adders connected to said buffer registers; and an output multiplexer connected to said second and fourth adders and to said mode input.
Claim 5
Dependent Claim
149 words
An integrated circuit for selectably performing matrix multiplication and convolution, comprising: multipliers arranged in a matrix of columns and rows on a substrate, each of said multipliers comprising: a coefficient register including a multiplexer selecting one of a hardwired input and an input coefficient and being serially loadable with a pseudo random test signal; a result register including a signal analysis serial output circuit; a data register producing the pseudo random test signal; and a signed multiplier connected to said coefficient register, result register and data register; column adders connected to said result registers in corresponding columns and located in corresponding columns; a convolution adder connected to said column adders and located in one of the columns; and means for selectably routing inputs and outputs to and from said multipliers, said column adders and said convolution adder responsive to selection of one of the matrix multiplication and the convolution.
Claim 6
Dependent Claim
149 words
An integrated circuit for selectably performing matrix multiplication and convolution, comprising: multipliers arranged in a matrix of columns and rows on a substrate, each of said multipliers comprising: a coefficient register including a multiplexer selecting one of a hardwired input and an input coefficient and being serially loadable with a pseudo random test signal; a result register including a signal analysis serial output circuit; a data register producing the pseudo random test signal; and a signed multiplier connected to said coefficient register, result register and data register; column adders connected to said result registers in corresponding columns and located in corresponding columns; a convolution adder connected to said column adders and located in one of the columns; and means for selectably routing inputs and outputs to and from said multipliers, said column adders and said convolution adder responsive to selection of one of the matrix multiplication and the convolution.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-15 | 1996-09-14 | 1997-03-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-15 | 2000-09-14 | 2001-03-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-15 | 2004-09-14 | 2005-03-16 | $7700.00 | Window Closed / Lapsed |