US5193157A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Piplined system includes a selector for loading condition code either from first or second condition code registers to program counter
Assignee: HP Inc
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Filing: 1991-09-27
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Granted: 1993-03-09
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Expires: 2011-09-27
Abstract
Abstract A method and apparatus is disclosed for control of a central processor in response to a branch instruction using two separate, subsequently updated condition codes. Computer architecture is provided wherein the condition codes which determine the processor state result from the execution of instructions prior to the currently executing instruction. When the preceding instructions are executed, condition codes are set and maintained in a first condition code register. The first condition code is transferred to the second condition code register, and the first condition code register is updated to reflect the result of the current instruction execution. Any condition code state such as a branch used by the third instruction is based on the condition code state maintained in the second condition code register.
Inventors
- 👤 Russell G. Barbour
- 👤 Carl A. Soeder
- 👤 Stephen J. Ciavaglia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:08
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3863; G06F9/30003; G06F9/30072; G06F9/30094
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
197 words
A computer system comprising: a processor; a first condition code register having a first port coupled to a first port of said processor; a second condition code register having a first port coupled to a second port of said first condition code register wherein said first condition code register is capable of holding a first condition code generated as a result of said processor executing a first instruction and wherein upon said processor executing a second instruction said first condition code is automatically transferred from said first condition code register to said second condition code register and a second condition code is automatically transferred to said first condition code register; a program counter unit having a first port; and a condition code selector, having a first port coupled to the second port of said first condition code register and a second port coupled to the second port of said second condition code register and a third port coupled to the first port of said program counter unit, for selectively providing a first one of said first and second condition codes to said program counter unit from a first one of said first and second condition code registers.
Claim 2
Dependent Claim
197 words
A computer system comprising: a processor; a first condition code register having a first port coupled to a first port of said processor; a second condition code register having a first port coupled to a second port of said first condition code register wherein said first condition code register is capable of holding a first condition code generated as a result of said processor executing a first instruction and wherein upon said processor executing a second instruction said first condition code is automatically transferred from said first condition code register to said second condition code register and a second condition code is automatically transferred to said first condition code register; a program counter unit having a first port; and a condition code selector, having a first port coupled to the second port of said first condition code register and a second port coupled to the second port of said second condition code register and a third port coupled to the first port of said program counter unit, for selectively providing a first one of said first and second condition codes to said program counter unit from a first one of said first and second condition code registers.
Claim 3
Dependent Claim
27 words
The computer system of claim 1 wherein said processor executes a branch instruction in response to said first condition code held in said second condition code register.
Claim 4
Independent Claim
164 words
A method of maintaining a series of condition codes in a condition code pipeline computer having a processor in communication with a first condition code register and a second condition code register in communication with said first condition code register, said method comprising the steps of: a. executing a first instruction by said processor; b. storing, in a first condition code register, a first condition code generated as a result of said processor executing said first instruction; c. executing a second instruction by said processor; d. automatically moving the first condition code generated as a result of said processor executing said first instruction from said first condition code register into a second condition code register; e. storing in the first condition code register a second condition code resulting from said processor executing said second instruction; and f. loading a selected one of the first or second condition codes from the corresponding one of the first or second condition code registers into a program counter.
Claim 5
Independent Claim
164 words
A method of maintaining a series of condition codes in a condition code pipeline computer having a processor in communication with a first condition code register and a second condition code register in communication with said first condition code register, said method comprising the steps of: a. executing a first instruction by said processor; b. storing, in a first condition code register, a first condition code generated as a result of said processor executing said first instruction; c. executing a second instruction by said processor; d. automatically moving the first condition code generated as a result of said processor executing said first instruction from said first condition code register into a second condition code register; e. storing in the first condition code register a second condition code resulting from said processor executing said second instruction; and f. loading a selected one of the first or second condition codes from the corresponding one of the first or second condition code registers into a program counter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-08 | 1996-09-07 | 1997-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-08 | 2000-09-07 | 2001-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-08 | 2004-09-07 | 2005-03-09 | $7700.00 | Window Closed / Lapsed |