EP0365187A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Apparatus for selective execution of instructions following a branch instruction
Assignee: Apollo Computer Inc
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Filing: 1989-10-06
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Granted: —
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Expires: 2009-10-06
Abstract
Abstract Computer apparatus providing selective execution of instructions following a branch instruction wherein the branch is executed in response to condition codes determined in preceding instructions. The instructions following the branch instructions, called branch shadows, include the branch instruction itself has the bit fields which specify the disposition of the shadow(s) in response to the previously determined code. The branch shadow instructions if executed will do so prior to the fetching of the branch target destination instruction. The resulting apparatus embodying the present invention, in particular, pipelined central processing units, provide enhanced performance by permitting useful instructions to be selectively executed while permitting the processor to incorporate delayed branching techniques.
Inventors
- 👤 Richard G. Bahr
- 👤 Stephen J. Ciavaglia
- 👤 John S. Yates, Jr.
- 👤 Hugh Lauer
- 👤 Peter Oppen
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 16:01
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3842; G06F9/30003; G06F9/30072
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
128 words
A method of efficiently processing a conditional manipulation of data in a pipelined processor, comprising the steps of: providing a first instruction type establishing a condition code having at least a true and a false state as a result of execution of said first instruction; providing a second instruction type subsequent to said first instruction selectably providing an execution branch to a destination instruction as a result of said condition code; and providing a third instruction type subsequent to said second instruction and being fetched by the execution unit of said processor before the destination instruction address is fetched, wherein said second instruction type further includes a control suffix appended thereto, and said third instruction type being selectively executed according to said control suffix and said condition code.
Claim 2
Independent Claim
128 words
A method of efficiently processing a conditional manipulation of data in a pipelined processor, comprising the steps of: providing a first instruction type establishing a condition code having at least a true and a false state as a result of execution of said first instruction; providing a second instruction type subsequent to said first instruction selectably providing an execution branch to a destination instruction as a result of said condition code; and providing a third instruction type subsequent to said second instruction and being fetched by the execution unit of said processor before the destination instruction address is fetched, wherein said second instruction type further includes a control suffix appended thereto, and said third instruction type being selectively executed according to said control suffix and said condition code.
Claim 3
Dependent Claim
93 words
The method of claim 1, wherein said step of providing a second instruction type includes providing a branch predicate; and said step of providing a third instruction type includes providing a branch shadow, wherein said condition code comprises at least one of the steps of: always executing said third instruction, never executing said third instruction, executing said third instruction conditioned on a true condition code and said second instruction executing said branch instruction, and executing said third instruction conditioned on a false condition code and a second instruction failure to execute a branch.
Claim 4
Dependent Claim
54 words
The method of claim 1 further including the step of providing a fourth instruction type intervening said first and said second instruction types comprising a number of instructions corresponding to the latency required by the second instruction type to respond to the state of the condition codes as set by said first instruction type.
Claim 5
Dependent Claim
16 words
The method of claim 3, wherein said fourth instruction type includes at least one no-operation instruction.
Claim 6
Dependent Claim
141 words
A computer execution unit, comprising: means for executing an instruction of a first instruction type establishing a condition code having at least a true and a false state as a result of the execution of an instruction of said first instruction type; means for executing an instruction of a second instruction type subsequent to said first instruction providing an execution branch to a destination instruction as a result of the state of said condition code; and means for executing an instruction of a third instruction type subsequent to said second instruction and being fetched before the destination instruction address is fetched, wherein said means for executing a third instruction type is responsive to a control suffix included in said second instruction, and said means for executing a third instruction type is operable according to said control suffix and said condition code.
Claim 7
Dependent Claim
141 words
A computer execution unit, comprising: means for executing an instruction of a first instruction type establishing a condition code having at least a true and a false state as a result of the execution of an instruction of said first instruction type; means for executing an instruction of a second instruction type subsequent to said first instruction providing an execution branch to a destination instruction as a result of the state of said condition code; and means for executing an instruction of a third instruction type subsequent to said second instruction and being fetched before the destination instruction address is fetched, wherein said means for executing a third instruction type is responsive to a control suffix included in said second instruction, and said means for executing a third instruction type is operable according to said control suffix and said condition code.
References Cited (Backward Citations)
No citation records indexed.
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