Analog signal extracting circuit

Claim 2

An analog signal extracting circuit comprising: a sampling gate for sampling an analog input voltage; a differential amplifier which receives an analog voltage outputted from said sampling gate, said differential amplifier including, a first p-channel MOS transistor having a source connected to a power supply and a gate connected to a first bias power supply, a second p-channel MOS transistor having a source connected to a drain of said first p-channel MOS transistor and a gate connected to said sampling gate, a third p-channel MOS transistor having a source connected to said drain of said first p-channel MOS transistor, a first n-channel MOS transistor having a gate and a drain each connected to a drain of said second p-channel MOS transistor and a source connected to ground, and a second n-channel MOS transistor having a drain connected to a drain of said third p-channel MOS transistor, a gate connected to said gate of said first n-channel MOS transistor and a source connected to the ground; and a buffer to which an output of said differential amplifier is applied, said buffer including, a third n-channel MOS transistor having a drain connected to said power supply, a gate connected to said drain of said third p-channel MOS transistor and a source connected to a gate of said third p-channel MOS transistor, a fourth n-channel MOS transistor having a drain connected to said source of said third n-channel MOS transistor, a gate connected to a second bias power supply and a source connected to the ground, and an output terminal connected to said source of said third n-channel MOS transistor.

Claim 3

An analog signal extracting circuit comprising: a sampling gate for sampling an analog input voltage; a differential amplifier which receives an analog voltage outputted from said sampling gate, said differential amplifier including, a first p-channel MOS transistor having a source connected to a power supply and a gate connected to a first bias power supply, a second p-channel MOS transistor having a source connected to a drain of said first p-channel MOS transistor and a gate connected to said sampling gate, a third p-channel MOS transistor having a source connected to said drain of said first p-channel MOS transistor, a first n-channel MOS transistor having a gate and a drain each connected to a drain of said second p-channel MOS transistor and a source connected to ground, and a second n-channel MOS transistor having a drain connected to a drain of said third p-channel MOS transistor, a gate connected to said gate of said first n-channel MOS transistor and a source connected to the ground; and a buffer to which an output of said differential amplifier is applied, said buffer including, a third n-channel MOS transistor having a drain connected to said power supply, a gate connected to said drain of said third p-channel MOS transistor and a source PG,14 connected to a gate of said third p-channel MOS transistor, a fourth n-channel MOS transistor having a drain connected to said source of said third n-channel MOS transistor, a gate connected to a second bias power supply and a source connected to the ground, and an output terminal connected to said source of said third n-channel MOS transistor and a back gate of said third n-channel MOS transistor being connected to said output terminal.

Claim 4

An analog signal extracting circuit comprising: a sampling gate for sampling an analog input voltage; a differential amplifier which receives an analog voltage outputted from said sampling gate, said differential amplifier including, a first p-channel MOS transistor having a source connected to a power supply and a gate connected to a first bias power supply, a second p-channel MOS transistor having a source connected to a drain of said first p-channel MOS transistor and a gate connected to said sampling gate, a third p-channel MOS transistor having a source connected to said drain of said first p-channel MOS transistor, a first n-channel MOS transistor having a gate and a drain each connected to a drain of said second p-channel MOS transistor and a source connected to ground, and a second n-channel MOS transistor having a drain connected to a drain of said third p-channel MOS transistor, a gate connected to said gate of said first n-channel MOS transistor and a source connected to the ground; and a buffer to which an output of said differential amplifier is applied, said buffer including, a third n-channel MOS transistor having a drain connected to said power supply, a gate connected to said drain of said third p-channel MOS transistor and a source PG,14 connected to a gate of said third p-channel MOS transistor, a fourth n-channel MOS transistor having a drain connected to said source of said third n-channel MOS transistor, a gate connected to a second bias power supply and a source connected to the ground, and an output terminal connected to said source of said third n-channel MOS transistor and a back gate of said third n-channel MOS transistor being connected to said output terminal.