Semiconductor device

Claim 2

A semiconductor memory device comprising: rectangular shaped semiconductor chip having a main surface and including a first pair of end sides that are relatively longer than a second pair thereof; two rectangular shaped memory cell array regions formed on said main surface and arranged apart from each other, wherein each memory cell array region has one pair of longer end sides are directioned in parallel to the longer end sides of the chip; two separate, peripheral circuit regions formed between said memory cell array regions on said main surface, wherein said two peripheral circuit regions are arranged in parallel with each other and each is extended adjacently along a relatively shorter end side of a respective one of said two rectangular shaped memory cell array regions; a plurality of bonding pads formed between said peripheral circuit regions, at a portion of said main surface away from an outer peripheral area thereof, and arranged along the direction of the shorter end sides of said memory cell array regions, wherein each one of said two peripheral circuit regions is formed between said plurality of bonding pads, in proximity thereto, and a respective one of said memory cell array regions; a plurality of leads, wherein each lead has an inner lead portion and an exposed outer lead portion extending outwardly from said inner lead portion, and wherein said inner lead portion has a front end part overlying said main surface of said semiconductor chip; an insulating film interposed between the front end parts of said inner lead portions of said plurality of leads and the main surface of said semiconductor chip, wherein aid insulating film is contacting the front end parts of said inner lead portions and the main surface of said semiconductor chip; means for electrically connecting the front end parts of said inner lead portions with said bonding pads, respectively; and a molding resin for molding said semiconductor chip, the inner lead portions of said plurality of leads and said insulating film.

Claim 3

A semiconductor memory device according to claim 1, wherein said bonding pads are arrayed substantially as two rows respectively aligned with said peripheral circuit regions in a direction substantially parallel to that of the shorter end sides of said memory cell array regions.

Claim 4

A semiconductor memory device according to claim 1, wherein said plurality of leads extend outwardly from only the longer end sides of said rectangular shaped semiconductor chip.

Claim 5

A semiconductor memory device according to claim 1, wherein said peripheral circuit regions and bonding pads are located at a central area of the main surface of said semiconductor chip.

Claim 6

A semiconductor memory device according to claim 1, wherein the front end parts of said inner lead portions are adjacently arranged to corresponding ones of said bonding pads, respectively.

Claim 7

A semiconductor memory device according to claim 1, wherein said means comprise bonding wires.

Claim 8

A semiconductor memory device according to claim 1, wherein said inner lead portions overlay the main surface of said semiconductor chip and are extended outwardly from said semiconductor chip.

Claim 9

A semiconductor memory device according to claim 2, wherein said plurality of leads extend outwardly from only the longer end sides of said rectangular shaped semiconductor chip.

Claim 10

A semiconductor memory device according to claim 8, wherein said peripheral circuit regions and bonding pads are located at a central area of the main surface of said semiconductor chip.

Claim 11

A semiconductor memory device according to claim 9, wherein the front end parts of said inner lead portions are adjacently arranged to corresponding ones of said bonding pads, respectively.

Claim 12

A semiconductor memory device according to claim 10, wherein said means comprise bonding wires.

Claim 13

A semiconductor memory device comprising: a rectangular shaped semiconductor chip having a main surface and including a first pair of end sides that are relatively longer than a second pair thereof; two rectangular shaped memory cell array regions formed on said main surface and arranged apart from each other, wherein each memory cell array region has one pair of end sides longer than another pair thereof, the pair of longer end sides are directioned in parallel to the longer end sides of the chip; two separate, peripheral circuit regions formed between said memory cell array regions on said main surface, wherein said two peripheral circuit regions are arranged in parallel with each other and each is extended adjacently along a relatively shorter end side of a respective one of said two rectangular shaped memory cell array regions; a plurality of bonding pads formed between said peripheral circuit regions, at a portion of said main surface away from an outer peripheral area thereof, and arranged along the direction of the shorter end sides of said memory cell array regions, wherein each one of said two peripheral circuit regions is formed between said plurality of bonding pads, in proximity thereto, and a respective one of said memory cell array regions; a plurality of leads, wherein each lead has an inner lead portion and an exposed outer lead portion extending outwardly from said inner lead portion, and wherein said inner lead portion has a front end part overlying said main surface of said semiconductor chip; a first insulating film interposed between the front end parts of said inner lead portions of said plurality of leads and the main surface of said semiconductor chip, wherein said first insulating film overlies the main surface of said semiconductor chip and is in contact with the front end parts of said inner lead portions; means for electrically connecting the front end parts of said inner lead portions with said bonding pads, respectively; and a molding resin for molding said semiconductor chip, the inner lead portions of said plurality of leads and said insulating film.

Claim 14

A semiconductor memory device comprising: a rectangular shaped semiconductor chip having a main surface and including a first pair of end sides that are relatively longer than a second pair thereof; two rectangular shaped memory cell array regions formed on said main surface and arranged apart from each other, wherein each memory cell array region has one pair of end sides longer than another pair thereof, the pair of longer end sides are directioned in parallel to the longer end sides of the chip; two separate, peripheral circuit regions formed between said memory cell array regions on said main surface, wherein said two peripheral circuit regions are arranged in parallel with each other and each is extended adjacently along a relatively shorter end side of a respective one of said two rectangular shaped memory cell array regions; a plurality of bonding pads formed between said peripheral circuit regions, at a portion of said main surface away from an outer peripheral area thereof, and arranged along the direction of the shorter end sides of said memory cell array regions, wherein each one of said two peripheral circuit regions is formed between said plurality of bonding pads, in proximity thereto, and a respective one of said memory cell array regions; a plurality of leads, wherein each lead has an inner lead portion and an exposed outer lead portion extending outwardly from said inner lead portion, and wherein said inner lead portion has a front end part overlying said main surface of said semiconductor chip; a first insulating film interposed between the front end parts of said inner lead portions of said plurality of leads and the main surface of said semiconductor chip, wherein said first insulating film overlies the main surface of said semiconductor chip and is in contact with the front end parts of said inner lead portions; means for electrically connecting the front end parts of said inner lead portions with said bonding pads, respectively; and a molding resin for molding said semiconductor chip, the inner lead portions of said plurality of leads and said insulating film.

Claim 15

A semiconductor memory device according to claim 12, wherein at least said memory cell array regions and said peripheral circuit regions are covered with a second insulating film.

Claim 16

A semiconductor memory device according to claim 13, wherein said second insulating film is a passivation film interposed between said first insulating film and the main surface of said semiconductor chip.

Claim 17

A semiconductor memory device according to claim 12, wherein said bonding pads are arrayed substantially as two rows respectively aligned with said peripheral circuit regions in a direction substantially parallel to that of the shorter end sides of said memory cell array regions.

Claim 18

A semiconductor memory device according to claim 12, wherein said plurality of leads extend outwardly from only the longer sides of said rectangular semiconductor chip.

Claim 19

A semiconductor memory device according to claim 15, wherein said plurality of leads extend outwardly from only the longer sides of said rectangular semiconductor chip.

Claim 20

A semiconductor memory device according to claim 17, wherein at least said memory cell array regions and said peripheral circuit regions are covered with a second insulating film,

Claim 21

A semiconductor memory device according to claim 18, wherein said second insulating film is a passivation film interposed between said first insulating film and the main surface of said semiconductor chip.

Claim 22

A semiconductor memory device comprising: a rectangular shaped semiconductor chip having a main surface and including a first pair of end sides that are relatively longer than a second pair thereof; two rectangular shaped memory cell array regions formed on said main surface and arranged apart from each other, wherein each memory cell array region has one pair of end sides longer than another thereof, the pair of longer end sides are directioned in parallel to the longer end sides of said semiconductor chip; a peripheral circuit region formed between said memory cell array regions on said main surface, wherein said peripheral circuit region is extended in a direction along the relatively shorter end sides of said memory cell array regions; a plurality of bonding pads formed between each one of said memory cell array regions and said peripheral circuit region, at a portion of said main surface substantially away from an outer peripheral area thereof, thereby effecting an arrangement of said plurality of bonding pads and said peripheral circuit region, in proximity thereto, between opposing relatively shorter end sides of said memory cell array regions; a plurality of leads, wherein each lead has an inner lead portion and an exposed outer lead portion extending outwardly from said inner lead portion, and wherein said inner lead portion has a front end part overlying the main surface of said semiconductor chip; an insulating film interposed between the front end parts of said dinner lead portion of said plurality of leads and the main surface of said semiconductor chip, wherein said insulating film is contacting the front end parts of said inner lead portions and said main surface of said semiconductor chip; means for electrically connecting the front end parts of said inner lead portions with said bonding pads, respectively; and a molding resin for molding said semiconductor chip, the inner lead portions of said plurality of leads and said insulating film.

Claim 23

A semiconductor memory device comprising: a rectangular shaped semiconductor chip having a main surface and including a first pair of end sides that are relatively longer than a second pair thereof; two rectangular shaped memory cell array regions formed on said main surface and arranged apart from each other, wherein each memory cell array region has one pair of end sides longer than another thereof, the pair of longer end sides are directioned in parallel to the longer end sides of said semiconductor chip; a peripheral circuit region formed between said memory cell array regions on said main surface, wherein said peripheral circuit region is extended in a direction along the relatively shorter end sides of said memory cell array regions; a plurality of bonding pads formed between each one of said memory cell array regions and said peripheral circuit region, at a portion of said main surface substantially away from an outer peripheral area thereof, thereby effecting an arrangement of said plurality of bonding pads and said peripheral circuit region, in proximity thereto, between opposing relatively shorter end sides of said memory cell array regions; a plurality of leads, wherein each lead has an inner lead portion and an exposed outer lead portion extending outwardly from said inner lead portion, and wherein said inner lead portion has a front end part overlying the main surface of said semiconductor chip; an insulating film interposed between the front end parts of said dinner lead portion of said plurality of leads and the main surface of said semiconductor chip, wherein said insulating film is contacting the front end parts of said inner lead portions and said main surface of said semiconductor chip; means for electrically connecting the front end parts of said inner lead portions with said bonding pads, respectively; and a molding resin for molding said semiconductor chip, the inner lead portions of said plurality of leads and said insulating film.

Claim 24

A semiconductor memory device according to claim 20, wherein said plurality of leads extend outwardly from only the longer end sides of said rectangular semiconductor chip.

Claim 25

A semiconductor memory device according to claim 20, wherein said peripheral circuit region and bonding pads are located at a central area of the main surface of said semiconductor chip.

Claim 26

A semiconductor memory device according to claim 20, wherein said bonding pads are arranged around said peripheral circuit region, and wherein a majority of said bonding pads, formed in proximity to said peripheral circuit region, are disposed away from said outer peripheral area of said main surface.

Claim 27

A semiconductor memory device according to claim 20, wherein the front end parts of said inner lead portions are adjacently arranged to corresponding ones of said bonding pads, respectively.

Claim 28

A semiconductor memory device according to claim 20, wherein said means comprise bonding wires.

Claim 29

A semiconductor memory device according to claim 20, wherein said inner lead portions overlay the main surface of said semiconductor chip and are extended outwardly form said semiconductor chip.

Claim 30

A semiconductor memory device according to claim 21, wherein said peripheral circuit region and bonding pads are located at a central area of the main surface of said semiconductor chip.

Claim 31

A semiconductor memory device according to claim 27, wherein the front end parts of said inner lead portions are adjacently arranged to corresponding ones of said bonding pads, respectively.

Claim 32

A semiconductor memory device comprising: a rectangular shaped semiconductor chip having a main surface and including a first pair of end sides that are relatively longer than a second pair thereof; two rectangular shaped memory cell array regions formed on said main surface and arranged apart from each other, wherein each memory cell array region has one pair of end sides longer than another thereof, the pair of longer end sides are directioned in parallel to the longer end sides of said semiconductor chip; a peripheral circuit region formed between said memory cell array regions on said main surface, wherein said peripheral circuit regions is extended in a direction along the relatively shorter end sides of said memory cell array regions; a plurality of bonding pads formed between each one of said memory cell array regions and said peripheral circuit region, at a portion of said main surface away from an outer peripheral area thereof, thereby effecting an arrangement of said plurality of bonding pads and said peripheral circuit region, in proximity thereto, between opposing relatively shorter end sides of said memory cell array regions; a plurality of leads, wherein each lead has an inner lead portion and an exposed outer lead portion extending outwardly from said inner lead portion, and wherein aid inner lead portion has a front end part overlying the main surface of said semiconductor chip; a first insulating film interposed between the front end parts of said inner lead portions of said plurality of leads and the main surface of said semiconductor chip, wherein said first insulating film overlies the main surface of said semiconductor chip and is contacting the front end parts of said inner lead portions; means for electrically connecting the front end parts of said inner lead portions with said bonding pads, respectively; and a molding resin for molding said semiconductor chip, the inner lead portions of said plurality of leads and said insulating film.

Claim 33

A semiconductor memory device comprising: a rectangular shaped semiconductor chip having a main surface and including a first pair of end sides that are relatively longer than a second pair thereof; two rectangular shaped memory cell array regions formed on said main surface and arranged apart from each other, wherein each memory cell array region has one pair of end sides longer than another thereof, the pair of longer end sides are directioned in parallel to the longer end sides of said semiconductor chip; a peripheral circuit region formed between said memory cell array regions on said main surface, wherein said peripheral circuit regions is extended in a direction along the relatively shorter end sides of said memory cell array regions; a plurality of bonding pads formed between each one of said memory cell array regions and said peripheral circuit region, at a portion of said main surface away from an outer peripheral area thereof, thereby effecting an arrangement of said plurality of bonding pads and said peripheral circuit region, in proximity thereto, between opposing relatively shorter end sides of said memory cell array regions; a plurality of leads, wherein each lead has an inner lead portion and an exposed outer lead portion extending outwardly from said inner lead portion, and wherein aid inner lead portion has a front end part overlying the main surface of said semiconductor chip; a first insulating film interposed between the front end parts of said inner lead portions of said plurality of leads and the main surface of said semiconductor chip, wherein said first insulating film overlies the main surface of said semiconductor chip and is contacting the front end parts of said inner lead portions; means for electrically connecting the front end parts of said inner lead portions with said bonding pads, respectively; and a molding resin for molding said semiconductor chip, the inner lead portions of said plurality of leads and said insulating film.

Claim 34

A semiconductor memory device according to claim 29, wherein at least said memory cell array regions and said peripheral circuit region are covered with a second insulating film.

Claim 35

A semiconductor memory device according to claim 50, wherein said second insulating film is a passivation film interposed between said first insulating film and the main surface of said semiconductor chip.

Claim 36

A semiconductor memory device according to claim 31, wherein said plurality of leads extend outwardly from only the longer end sides of said rectangular semiconductor chip.

Claim 37

A semiconductor memory device according to claim 29, wherein said plurality of leads extend outwardly from only the longer end sides of said rectangular semiconductor chip.

Claim 38

A semiconductor memory device according to claim 33, wherein said peripheral circuit region and bonding pads are located at a central area of the main surface of said semiconductor chip.