Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
166 words
A circuit which comprises: (a) a plurality of logic elements, each logic element comprising: (i) a first input; (ii) a memory element; (iii) means for selectively storing the value of said first input in said memory element; (b) a plurality of OR gates, at least one of said OR gates having at least one second input and having a first output, said first output being connected to at least one of said first inputs; (c) a plurality of AND gates, at least one of said AND gates having at least one third input, and having a second output, said second output being connected to at least one of said second inputs; (d) means for selectively connecting said memory elements to said third inputs; (e) means for selectively connecting the inverses of said memory elements to said third inputs; (f) means for selecting one of said logic elements; and (g) means responsive to said selecting means for activating said selective storing means of said selected logic element.
Claim 2
Dependent Claim
166 words
A circuit which comprises: (a) a plurality of logic elements, each logic element comprising: (i) a first input; (ii) a memory element; (iii) means for selectively storing the value of said first input in said memory element; (b) a plurality of OR gates, at least one of said OR gates having at least one second input and having a first output, said first output being connected to at least one of said first inputs; (c) a plurality of AND gates, at least one of said AND gates having at least one third input, and having a second output, said second output being connected to at least one of said second inputs; (d) means for selectively connecting said memory elements to said third inputs; (e) means for selectively connecting the inverses of said memory elements to said third inputs; (f) means for selecting one of said logic elements; and (g) means responsive to said selecting means for activating said selective storing means of said selected logic element.
Claim 3
Dependent Claim
66 words
A circuit as recited in claim 1, wherein said selecting means comprises: (a) a plurality of means, one associated with each of said logic elements, for comparing whether said first input is equal to the state of said memory element; (b) means for selecting one of said logic elements for which said comparing means indicates inequality, when at least one of said comparing means indicates inequality.
Claim 4
Dependent Claim
28 words
A circuit as recited in claim 2, wherein said comparing means comprises an EXCLUSIVE OR gate having inputs connected to said memory element and to said first input.
Claim 5
Dependent Claim
19 words
A circuit as recited in claim 2, wherein at least one of said logic elements comprises a D-type flip-flop.
Claim 6
Dependent Claim
19 words
A circuit as recited in claim 2, wherein at least one of said logic elements comprises a tap-delay line.
Claim 7
Dependent Claim
21 words
A circuit as recited in claim 2, wherein each of said first inputs is connected to one of said first outputs.
Claim 8
Dependent Claim
23 words
A circuit as recited in claim 2, wherein each of said second inputs is connected to at least one of said second outputs.
Claim 9
Dependent Claim
26 words
A circuit as recited in claim 2, wherein said selective connecting means corresponds to a set of rules for a knowledge base and a logic system.
Claim 10
Dependent Claim
15 words
A circuit as recited in claim 8, wherein said logic system is conventional truth-table logic.
Claim 11
Dependent Claim
16 words
A circuit as recited in claim 8, wherein said logic system is a truth maintenance system.
Claim 12
Dependent Claim
20 words
A circuit as recited in claim 2, additionally comprising means for outputting the values of each of said memory elements.
Claim 13
Dependent Claim
20 words
A circuit as recited in claim 2, additionally comprising means for outputting the values of each of said first inputs.
Claim 14
Dependent Claim
24 words
A circuit as recited in claim 2, additionally comprising means for selectively clamping at least one of said first inputs to a desired value.