Patent US5175833A successfully refreshed from Google Patents.
US5175833A
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Apparatus for determining relative position of a cache memory in a cache memory array
Assignee: Intel Corp
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Filing: 1990-06-07
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Granted: 1992-12-29
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Expires: 2010-06-07
Abstract
Abstract A cache memory which includes a cache controller formed on a single substrate. A plurality of the identical memories may be used in an array. The memories themselves determined how many other memories are in an array and each of their relative positions in the array. From this information, each memory sets the range of its set fields and the size of its tag fields. This is done on reset with the configuration information being distributed among the memories themselves, without being centrally stored, and in a manner transparent to the software.
Inventors
- 👤 Eran Yarkoni
- 👤 Zvi Netzer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:23
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0864; G06F2212/00; G06F2212/60; G06F2212/601
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
121 words
In a cache memory, an improvement for determining the relative position of said cache memory in an array which includes other cache memories comprising: a first terminal for receiving an externally applied configuration signal; a second terminal for receiving a reset signal; a third terminal for receiving a timing signal; a fourth terminal for providing and receiving a ready signal; circuit means coupled to said first, second, third and fourth terminals for sensing said configuration signal upon receiving said reset signal, and for; while said configuration signal is a first predetermined signal, counting ready signals under control of said timing signal; while said configuration signal is a second predetermined signal again sensing said configuration signal under control of said timing signal.
Claim 2
Dependent Claim
121 words
In a cache memory, an improvement for determining the relative position of said cache memory in an array which includes other cache memories comprising: a first terminal for receiving an externally applied configuration signal; a second terminal for receiving a reset signal; a third terminal for receiving a timing signal; a fourth terminal for providing and receiving a ready signal; circuit means coupled to said first, second, third and fourth terminals for sensing said configuration signal upon receiving said reset signal, and for; while said configuration signal is a first predetermined signal, counting ready signals under control of said timing signal; while said configuration signal is a second predetermined signal again sensing said configuration signal under control of said timing signal.
Claim 3
Dependent Claim
48 words
The improvement defined by claim 1 wherein said cache memory is coupled to a system bus and a local bus and if said configuration signal is said first predetermined signal, said cache memory enabling a system bus driving means for driving bus signals on to said system bus.
Claim 4
Dependent Claim
92 words
The improvement defined by claim 1 or claim 2 wherein if said configuration signal is said second predetermined signal, said circuit means performing a second sensing of said configuration signal under control of said timing signal, and, if after again being sensed, said configuration signal is said first predetermined signal, providing a ready signal on said fourth terminal and then counting ready signals received on said fourth terminal; if said configuration signal is said second predetermined signal then performing a third sensing of said configuration signal under control of said timing signal.
Claim 5
Dependent Claim
28 words
The improvement defined by claim 3 wherein if said third sensing of said configuration signal senses said second predetermined signal, providing a ready signal on said fourth terminal.
Claim 6
Dependent Claim
15 words
The improvement defined by claim 4 wherein said first predetermined signal is a ground signal.
Claim 7
Dependent Claim
15 words
The improvement defined by claim 5 wherein said second predetermined signal is a positive potential.
Claim 8
Dependent Claim
142 words
In a cache memory for coupling to a local bus and a system bus, an improvement comprising: control means coupled to receive a reset signal, a timing signal, and configuration signal, and coupled to receive and provide a ready signal, said control means on receiving of said reset signal providing at least one control means signal indicating if said cache memory is the primary memory in an array of other cache memories; and, bus driving means coupled to said control means for providing bus signals for said local bus and said system bus, said bus driving means enabling a predetermined bus signal if said control means signal indicates said cache memory is said primary memory and said bus driving means for disabling said predetermined bus signal if said control means signal indicates that said cache memory is other than said primary memory.
Claim 9
Dependent Claim
142 words
In a cache memory for coupling to a local bus and a system bus, an improvement comprising: control means coupled to receive a reset signal, a timing signal, and configuration signal, and coupled to receive and provide a ready signal, said control means on receiving of said reset signal providing at least one control means signal indicating if said cache memory is the primary memory in an array of other cache memories; and, bus driving means coupled to said control means for providing bus signals for said local bus and said system bus, said bus driving means enabling a predetermined bus signal if said control means signal indicates said cache memory is said primary memory and said bus driving means for disabling said predetermined bus signal if said control means signal indicates that said cache memory is other than said primary memory.
Claim 10
Dependent Claim
30 words
The improvement defined by claim 7 wherein said bus driving means provides a signal to said system bus indicating a miss in said memory independent of said control means signal.
Claim 11
Dependent Claim
21 words
The improvement defined by claim 7 wherein said bus driving means provides said ready signal independent of said control means signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-29 | 1996-06-29 | 1996-12-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-29 | 2000-06-29 | 2000-12-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-29 | 2004-06-29 | 2004-12-29 | $7700.00 | Window Closed / Lapsed |