Patent US5175707A successfully refreshed from Google Patents.
US5175707A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device having a driving circuit provided in association with a high speed sense amplifier circuit
Assignee: NEC Electronics Corp
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Filing: 1990-10-22
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Granted: 1992-12-29
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Expires: 2010-10-22
Abstract
Abstract A semiconductor memory device comprises memory cell array, bit line pairs respectively coupled to the columns of the memory cells, sense amplifier circuits operative to increase small differences in voltage level on the bit line pairs, first and second voltage lines supplying a high voltage level and the ground voltage level through the sense amplifier circuits to the bit line pairs for increasing the small difference, and a driving circuit operative to activate the sense amplifier circuits, wherein the driving circuit comprises an equalizing circuit for equalizing the first and second voltage lines to an intermediate voltage level, a first transistor coupled between the first voltage line and a source of an external voltage level higher than the high voltage level, a second transistor providing a conduction path between a source of the second voltage level and the second voltage line in the presence of a control signal and isolating the second voltage line from the source of the second voltage level in the absence of the control signal, and a control circuit causing the first transistor to produce the high voltage level in the presence of another control signal and to isolate the first voltage line from the source of the external voltage level in the absence of the control signal.
Inventors
- 👤 Tatsunori Murotani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:11
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4091
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
368 words
A semiconductor memory device comprising: a) a plurality of memory cells arranged in rows and columns and respectively storing data bits, b) a plurality of bit line pairs respectively provided in association with the columns of said memory cells, said data bits read out from said memory cells producing small differential voltage levels on said bit line pairs, respectively, c) a plurality of sense amplifier circuits respectively coupled to said bit line pairs and operative to develop said small differential voltage levels, thereby supplying large differential voltage levels to said bit line pairs, said large differential voltage levels being approximately equal to a difference between first and second voltage levels, d) first and second voltage lines supplying said first and second voltage levels through said sense amplifier circuits to said bit line pairs, and e) a driving circuit responsive to at least first, second and third control signals and operative to activate said sense amplifier circuits for producing said large differential voltage levels, said driving circuit comprising (e-1) an equalizing circuit for equalizing said first and second voltage lines to an intermediate voltage level between said first and second voltage levels in the presence of said first control signal and for isolating said first and second voltage lines from a source of said intermediate voltage level in the absence of said first control signal, (e-2) a first transistor coupled between a source of a third voltage level and said first voltage line, said third voltage level being outside a voltage range between said first and second voltage levels, (e-3) a second transistor for providing a conduction path between a source of said second voltage level and said second voltage line in the presence of said second control signal and for isolating said second voltage line from said source of said second voltage level in the absence of said second control signal, and (e-4) a control circuit for allowing said first transistor to produce said first voltage level from said third voltage level in the presence of said third control signal and for causing said first transistor to isolate said first voltage line from said source of said third voltage level in the absence of said third control signal.
Claim 2
Dependent Claim
368 words
A semiconductor memory device comprising: a) a plurality of memory cells arranged in rows and columns and respectively storing data bits, b) a plurality of bit line pairs respectively provided in association with the columns of said memory cells, said data bits read out from said memory cells producing small differential voltage levels on said bit line pairs, respectively, c) a plurality of sense amplifier circuits respectively coupled to said bit line pairs and operative to develop said small differential voltage levels, thereby supplying large differential voltage levels to said bit line pairs, said large differential voltage levels being approximately equal to a difference between first and second voltage levels, d) first and second voltage lines supplying said first and second voltage levels through said sense amplifier circuits to said bit line pairs, and e) a driving circuit responsive to at least first, second and third control signals and operative to activate said sense amplifier circuits for producing said large differential voltage levels, said driving circuit comprising (e-1) an equalizing circuit for equalizing said first and second voltage lines to an intermediate voltage level between said first and second voltage levels in the presence of said first control signal and for isolating said first and second voltage lines from a source of said intermediate voltage level in the absence of said first control signal, (e-2) a first transistor coupled between a source of a third voltage level and said first voltage line, said third voltage level being outside a voltage range between said first and second voltage levels, (e-3) a second transistor for providing a conduction path between a source of said second voltage level and said second voltage line in the presence of said second control signal and for isolating said second voltage line from said source of said second voltage level in the absence of said second control signal, and (e-4) a control circuit for allowing said first transistor to produce said first voltage level from said third voltage level in the presence of said third control signal and for causing said first transistor to isolate said first voltage line from said source of said third voltage level in the absence of said third control signal.
Claim 3
Dependent Claim
80 words
A semiconductor memory device as set forth in claim 1, in which said equalizing circuit comprises a third transistor coupled between said source of said intermediate voltage level and said first voltage line, a fourth transistor coupled between said source of said intermediate voltage level and said second voltage line and a fifth transistor coupled between said first and second transistors, and in which said first control signal is supplied to gate electrodes of said third, fourth and fifth transistors.
Claim 4
Dependent Claim
106 words
A semiconductor memory device as set forth in claim 1, in which said control circuit comprises an operational amplifier circuit having an inverting node and a noninverting node coupled to said first voltage line, a third transistor coupled between the inverting node and a source of a reference voltage level equal to said first voltage level, a fourth transistor coupled between the inverting node and said source of said second voltage level, and an inverter circuit coupled to a gate electrode of said fourth transistor, and in which said third control signal is supplied to said inverter circuit and a gate electrode of said third transistor.
Claim 5
Dependent Claim
129 words
A semiconductor memory device as set forth in claim 1, in which said control circuit comprises an operational amplifier circuit having an inverting node and a noninverting node coupled to said first voltage line, a third transistor coupled between the inverting node and a source of a reference voltage level equal to said first voltage level, a fourth transistor coupled between the inverting node and said source of said second voltage level, and a fifth transistor coupled between the inverting node and a source of another reference voltage level which is different in magnitude from said source of said reference voltage level, and in which said third control signal consisting of a plurality of clock signals is supplied to the gate electrodes of said third, fourth and fifth transistors.
References Cited (Backward Citations)
US4951256A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-29 | 1996-06-29 | 1996-12-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-29 | 2000-06-29 | 2000-12-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-29 | 2004-06-29 | 2004-12-29 | $7700.00 | Window Closed / Lapsed |