Patent US5173875A successfully refreshed from Google Patents.
US5173875A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1990-11-08
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Granted: 1992-12-22
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Expires: 2010-11-08
Abstract
Abstract There is enclosed a semiconductor memory device having an internal circuit including a plurality of memory cells which can store data thereinto, respectively, to output, as a first output signal, data in a memory cell selected by an address signal, and an output circuit adapted to receive the first output signal to output a second output signal. Power from the same external power supply is delivered to the internal circuit and the output circuit through power supply terminals, and power supply wirings. The power is delivered to the internal circuit through a resistor formed in the middle of the power supply wirings.
Inventors
- 👤 Kenji Komatsu
- 👤 Teruyuki Hiyoshi
- 👤 Tohru Yoshikawa
- 👤 Kaoru Nakagawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:22
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C5/00; G11C5/14; G11C5/147; G11C7/1078; G11C2207/00; G11C2207/10; G11C2207/108
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
103 words
A semiconductor memory device comprising: an internal circuit including a plurality of memory cells which can store data respectively, to output, as a first output signal, data in a memory cell selected by an address signal, and an output circuit adapted to receive said first output signal to produce a second output signal corresponding to the external output, power from the same external power supply being delivered to said internal circuit and said output circuit through power supply terminals, and power supply wirings, said power being delivered to said internal circuit through a resistor formed in the middle of said power supply wirings.
Claim 2
Dependent Claim
103 words
A semiconductor memory device comprising: an internal circuit including a plurality of memory cells which can store data respectively, to output, as a first output signal, data in a memory cell selected by an address signal, and an output circuit adapted to receive said first output signal to produce a second output signal corresponding to the external output, power from the same external power supply being delivered to said internal circuit and said output circuit through power supply terminals, and power supply wirings, said power being delivered to said internal circuit through a resistor formed in the middle of said power supply wirings.
Claim 3
Dependent Claim
28 words
A device as set forth in claim 1, wherein the power from said external power supply is directly delivered to said output circuit through said power supply wiring.
Claim 4
Dependent Claim
16 words
A device as set forth in claim 1, wherein said output circuit includes a buffer circuit.
Claim 5
Dependent Claim
77 words
A device as set forth in claim 1, wherein said power supply terminal includes first separate power supply terminals for delivering power to said output circuit, and second separate power supply terminals for delivering power to said internal circuit, said power supply wiring including first separate power supply wirings for connecting said first power supply terminals and said output circuit, and second separate power supply wirings for connecting said second power supply terminals and said internal circuit.
Claim 6
Dependent Claim
52 words
A device as set forth in claim 1, wherein said power supply wiring include first power supply wirings for connecting said power supply terminals and said output circuit, which are branched from said power supply terminals, respectively, and second power supply wirings for connecting said power supply terminals and said internal circuit.
Claim 7
Dependent Claim
103 words
A device as set forth in claim 1, wherein said power supply terminal includes high voltage side power supply terminals connected to a high voltage side of said external power supply, and low voltage side power supply terminals connected to a low voltage side of said external power supply, said power supply wiring including high voltage side power supply wirings for connecting said high voltage side power supply terminals to said output circuit and said internal circuit, respectively, and low voltage side power supply wirings for connecting said low voltage side power supply terminals to said output circuit and said internal circuit, respectively.
Claim 8
Dependent Claim
101 words
A device as set forth in claim 1, wherein said power supply terminal includes high voltage side power supply terminal connected to a high voltage side of said external power supply, and low voltage side power supply terminal connected to a low voltage side of said external power supply, said power supply wiring including high voltage side power supply wirings for connecting said high voltage side power supply terminal to said output circuit and said internal circuit, and low voltage side power supply wirings for connecting said low voltage side power supply terminal to said output circuit and said internal circuit.
Claim 9
Dependent Claim
37 words
A device as set forth in claim 1, wherein said internal circuit and said output circuit are formed in the same semiconductor chip, each of said power supply terminals including a conductive pad formed on said chip.
Claim 10
Dependent Claim
52 words
A device as set forth in claim 4, wherein said internal circuit and said output circuit are formed in the same semiconductor chip, said first and second power supply wirings being formed on said chip, each of said first and second power supply terminals including a conductive pad formed on said chip.
Claim 11
Dependent Claim
49 words
A device as set forth in claim 5, wherein said internal circuit and said output circuit are formed in the same semiconductor chip, said first and second power supply wirings being formed on said chip, each of said power supply terminals including a conductive pad formed on said chip.
References Cited (Backward Citations)
US5045726A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-22 | 1996-06-22 | 1996-12-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-22 | 2000-06-22 | 2000-12-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-22 | 2004-06-22 | 2004-12-22 | $7700.00 | Window Closed / Lapsed |