Binary data encoding and decoding using a rate 2/5 (2,18,2) code

Claim 2

A data storage system in which data is written on and read from a data storage medium, comprising: an encoder that receives digital electrical signals representing serial binary input data and comprises: (i) a serial-to-parallel converter that converts two sequentially chosen bits of binary input data into two parallel bits; (ii) a register for holding a five-bit current-state denoting vector of the encoder; and (iii) a read only memory lookup table that, from an address specified by said two parallel bits and five-bit current-state-denoting vector, generates a five-bit next state vector that is supplied to and updates the register and also generates a five-bit codeword chosen from one of the following eight possible codewords: 00000, 00001, 00010, 00100, 01000, 10000, 10010, 01001 for encoding the binary input data into a (2, 18, 2) code; (iv) a five-bit parallel-to serial converter for converting the five-bit codeword into electrical signals as a string of serial (2, 18, 2) binary encoded data; and a transducer for writing the serial (2, 18, 2) binary encoded data onto the medium.

Claim 3

The system of claim 1, characterized in that the lookup table constitutes a finite state machine that has the following 25 states and paths between states for converting the binary input data into the string of serial (2, 18, 2) binary encoded data, the two sequentially chosen input bits being 00, 01, 10 or 11, and the next state and five-bit codeword being as denoted by hyphenated sequences below: ______________________________________ Current INPUT DATA State 00 01 10 11 ______________________________________ 01 04-00100 17-00100 18-00100 19-00100 02 06-00100 20-00100 21-00100 22-00100 03 01-00100 02-00100 03-00100 05-00100 04 13-00000 14-00000 15-00000 16-00000 05 08-00000 11-00000 23-00000 10-00000 06 04-00001 05-00001 06-00001 07-00001 07 01-00001 02-00001 03-00001 09-00000 08 13-01000 14-01000 15-01000 16-01000 09 04-00000 17-00000 18-00000 19-00000 10 20-00000 21-00000 06-00000 22-00000 11 08-01000 10-01000 11-01000 23-01000 12 01-00000 02-00000 03-00000 24-00000 13 13-00010 14-00010 15-00010 16-00010 14 09-00010 10-00010 11-00010 12-00010 15 01-01001 02-01001 03-01001 08-00010 16 04-01001 05-01001 06-01001 07-01001 17 04-10000 17-10000 18-10000 19-10000 18 06-10000 20-10000 21-10000 22-10000 19 01-10000 02-10000 03-10000 05-10000 20 09-10010 10-10010 11-10010 12-10010 21 13-10010 14-10010 15-10010 16-10010 22 01-00001 02-00001 03-00001 08-10010 23 01-00000 02-00000 03-00000 09-01000 24 08-00000 11-00000 23-00000 25-00000 25 20-00000 21-00000 18-00000 19-00000 ______________________________________

Claim 4

The system of claim 1, wherein the transducer comprises a diode laser and the data storage system is an optical disk system.

Claim 5

The system of claim 1, wherein the transducer comprises a magnetic recording head and the data storage system is a magnetic recording system.

Claim 6

The system of claim 1, including a sliding block decoder that decodes the string of serial (2, 18, 2) binary encoded data read from the medium into the serial binary input data, and comprises: (i) a first shift register for converting the string of (2, 18, 2) serial binary encoded data into four five-bit codewords; (ii) codeword reassignment logic circuitry for converting each five-bit codeword into a reassigned three-bit codeword representation; (iii) an address register means comprising three four-bit shift registers for collecting sets of four adjacent three-bit codeword representations; (iv) a read only memory look up table for converting each reassigned three-bit codeword representation to a two-bit output corresponding to a then current set of four three-bit codeword representations; and (v) means including a second register, a multiplexor and a third register connected in series for converting successive two-bit outputs into the serial binary data.

Claim 7

A sliding block decoder for decoding into serial binary data a string of serial rate m/n code data read from a data recording medium, said apparatus comprising: a first shaft register for converting the serial string to j n-bit codewords; codeword reassignment logic circuitry for converting each n-bit codeword into a reassigned k-bit codeword representation, where k<n; address register means comprising k j-bit shift registers for collecting sets of j adjacent k-bit codeword representations; a read only memory look up table for converting each reassigned k-bit codeword representation to an m-bit output corresponding to a then current set of j k-bit codeword representations; and means including a second register, a multiplexor and a third register connected in series for converting successive m-bit outputs into the serial binary data.

Claim 8

A sliding block decoder for decoding into serial binary data a string of serial rate m/n code data read from a data recording medium, said apparatus comprising: a first shaft register for converting the serial string to j n-bit codewords; codeword reassignment logic circuitry for converting each n-bit codeword into a reassigned k-bit codeword representation, where k<n; address register means comprising k j-bit shift registers for collecting sets of j adjacent k-bit codeword representations; a read only memory look up table for converting each reassigned k-bit codeword representation to an m-bit output corresponding to a then current set of j k-bit codeword representations; and means including a second register, a multiplexor and a third register connected in series for converting successive m-bit outputs into the serial binary data.

Claim 9

The decoder of claim 6, wherein m=2, k=3, j=4 and n=5 for decoding a rate 2/5 (2, 18, 2) run length limited code.