Method and apparatus for encoding and decoding binary data

Claim 2

Apparatus for encoding binary data in the form of serially occurring binary data bits into a series of signal transitions in order to effect high density data transmission comprising: means for converting each said data bit in series into a predetermined one of a plurality of code words according to five states of said means for converting, each code word including three code bits, wherein a "1" code bit signifies a signal transition and a "0" code bit signifies no signal transition, such that 2, 4, 6, or 8 "0" code bits are generated between each "1" code bit; and means for transmitting each said code word from said conversion means.

Claim 3

The encoding apparatus of claim 1 further comprising: means for determining when a first data bit is coupled to said conversion means, said conversion means including means responsive to said first data bit determination means for generating a first state code word when said first data bit has a first polarity and for generating a fifth state code word when said first data bit has a second polarity, means responsive to being in said first state and a next data bit for generating another said first state code word when said next data bit has a first polarity and for generating a second state code word when said next data bit has a second polarity, means responsive to being in said second state and a next data bit for generating a third state code word when said next data bit has a first polarity and for generating a fourth state code word when said next data bit has a second polarity, means responsive to being in said third state and a next data bit for generating another said third state code word when said next data bit has a first polarity and for generating said fourth state code word when said next data bit has a second polarity, means responsive to being in said fourth state and a next data bit for generating said first state code word when said next data bit has a first polarity and for generating said fifth state code word when said next data bit has a second polarity, and means responsive to being in said fifth state and a next data bit for generating said first state code word when said next data bit has a first polarity and for generating another said fifth state code word when said next data bit has a second polarity.

Claim 4

The encoding apparatus of claim 2 wherein said first state code word comprises code bits 001, said second state code word comprises code bits 000, said third state code word comprises code bits 010, said fourth state code word comprises code bits 000, and said fifth state code word comprises code bits 100.

Claim 5

The encoding apparatus of claim 1 wherein said conversion means further comprises means for periodically generating a synchronization signal having at least ten successive "0" bits.

Claim 6

Apparatus for encoding binary data in the form of serially occurring binary data bits into a series of signal transitions recorded on a medium comprising: means for converting each said data bit in series into a predetermined one of four code words according to five states of said means for converting, each code word including three code bits, wherein a "1" code bit signifies a signal transition and a "0" code bit signifies no signal transition, such that 2, 4, 6, or 8 "0" code bits are generated between each "1" code bit; and means for recording each said code word at a successive location on said medium.

Claim 7

Apparatus for encoding binary data in the form of serially occurring binary data bits into a series of signal transitions recorded on a medium comprising: means for converting each said data bit in series into a predetermined one of four code words according to five states of said means for converting, each code word including three code bits, wherein a "1" code bit signifies a signal transition and a "0" code bit signifies no signal transition, such that 2, 4, 6, or 8 "0" code bits are generated between each "1" code bit; and means for recording each said code word at a successive location on said medium.

Claim 8

The encoding apparatus of claim 5 further comprising: means for determining when a first data bit is coupled to said conversion means, said conversion means including means responsive to said first data bit determination means for generating a first state code word when said first data bit has a first polarity and for generating a fifth state code word when said first data bit has a second polarity. means responsive to being in said first state and a next data bit for generating another said first state code word when said next data bit has a first polarity and for generating a second state code word when said next data bit has a second polarity, means responsive to being in said second state and a next data bit for generating a third state code word when said next data bit has a first polarity and for generating a fourth state code word when said next data bit has a second polarity, means responsive to being in said third state and a next data bit for generating another said third state code word when said next data bit has a first polarity and for generating said fourth state code word when said next data bit has a second polarity. means responsive to being in said fourth state and a next data bit for generating said first state code word when said next data bit has a first polarity and for generating said fifth state code word when said next data bit has a second polarity, and means responsive to being in said fifth state and a next data bit for generating said first state code word when said next data bit has a first polarity and for generating another said fifth state code word when said next data bit has a second polarity.

Claim 9

The encoding apparatus of claim 6 wherein said first state code word comprises code bits 001, said second state code word comprises code bits 000, said third state code word comprises code bits 010, said fourth state code word comprises code bits 000, and said fifth state code word comprises code bits 100.

Claim 10

The encoding apparatus of claim 5 wherein said conversion means further comprises means for generating a synchronization signal having at least ten successive "0" bits.

Claim 11

The encoding apparatus of claim 5 further including decoding means for reading said code words from said medium and for reconverting said code words into binary data.

Claim 12

The apparatus of claim 9 wherein said conversion means further comprises means for generating a synchronization signal having at least ten successive "0" bits and wherein said decoding means includes means for detecting said synchronization signal on said medium.

Claim 13

The apparatus of claim 5 wherein said medium comprises a magnetic recording surface, said recording means including means for generating magnetic flux transitions on said magnetic surface as a function of the generation of each said "1" code bit.

Claim 14

The encoding apparatus of claim 5 wherein said medium comprises an optical disk having a recording surface and a laser light source, said recording means including means for moving the laser light source with respect to a track defined on the surface of said optical disk, means for causing said laser light source to generate successive pulses of laser light energy of predetermined duration as a function of said code bits, and means for focusing said laser light energy onto the surface of said optical disk such that each said pulse alters the reflectivity of a selected region of said medium.

Claim 15

The encoding apparatus of claim 12 wherein said conversion means further comprises means for converting said code words into polarized code words, each polarized code word including three polarized code bits, wherein a "1" polarized code bit signifies the on time of said pulse of laser light energy and a "0" polarized code bit signifies a laser off time, said recording means responsive to said polarized code words for forming regions of altered reflectivity in said medium having durations equal to 3, 5, 7 and 9 on times of said laser, and wherein the duration of the laser off times between each said region of altered reflectivity is set to have a duration of 3, 5, 7 and 9 on times.

Claim 16

The apparatus of claim 13 wherein said laser on time is normally equal to one-third of the length of the minimum region of altered reflectivity formed by said pulse of laser light energy.

Claim 17

The apparatus of claim 14 wherein said laser on time is adjustable as a function of the characteristics of the medium.

Claim 18

The apparatus of claim 14 wherein said regions of altered reflectivity having on time durations of 5, 7 and 9 on times are formed by generating a pulse of laser light energy during alternate intervals of laser on time for the duration of the writing of a given region of altered reflectivity on said medium.

Claim 19

The apparatus of claim 16 wherein said region of reflectivity having a duration of 5 laser on time intervals is formed by generating a pulse of laser light energy during the second and fourth laser on time interval, wherein said region of reflectivity having a duration of 7 laser on time intervals is formed by generating a pulse of laser light energy during the second, fourth and sixth laser on time interval, and wherein said region of altered reflectivity having a duration of 9 laser on time intervals is formed by generating a pulse of laser light energy during the second, fourth, sixth and eighth laser on time interval.

Claim 20

Apparatus for receiving a series of signal transitions in a data transmission and for decoding binary data from said signal transitions comprising: means for detecting each said signal transition in said data transmission; means for generating a periodic clock signal as a function of the occurrence of said signal transitions; means responsive to said signal transitions for detecting a synchronization signal; means for converting each series of three code bits defined with respect to said synchronization signal into a predetermined data bit, wherein a "1" code bit signifies a signal transition and a "0" code bit signifies the absence of a signal transition when said clock signal indicates a signal transition clock time, and wherein 2, 4, 6, or 8 "0" code bits exist between each "1" code bit, each said series of three code bits defining a predetermined one of four code words, the current and previous said code word determining whether a data bit of a first polarity or a data bit of a second polarity is generated by said decoding means; and means for outputting each said decoded data bit.

Claim 21

Apparatus for receiving a series of signal transitions in a data transmission and for decoding binary data from said signal transitions comprising: means for detecting each said signal transition in said data transmission; means for generating a periodic clock signal as a function of the occurrence of said signal transitions; means responsive to said signal transitions for detecting a synchronization signal; means for converting each series of three code bits defined with respect to said synchronization signal into a predetermined data bit, wherein a "1" code bit signifies a signal transition and a "0" code bit signifies the absence of a signal transition when said clock signal indicates a signal transition clock time, and wherein 2, 4, 6, or 8 "0" code bits exist between each "1" code bit, each said series of three code bits defining a predetermined one of four code words, the current and previous said code word determining whether a data bit of a first polarity or a data bit of a second polarity is generated by said decoding means; and means for outputting each said decoded data bit.

Claim 22

In a system for storing binary bode bits stored on a medium as a series of signal transitions, an apparatus for decoding binary data from said signal transitions comprising: means for detecting each said signal transition on a selected segment of said medium; means for generating a periodic clock signal as a function of the occurrence of said signal transitions; means responsive to said signal transitions for detecting a synchronization signal; means for converting each series of three code bits defined with respect to said synchronization signal into a predetermined data bit, wherein a "1" code bit signifies a signal transition and a "0" code bit signifies the absence of a signal transition when said clock signal indicates a signal transition clock time, and wherein 2, 4, 6, or 8 "0" code bits exist between each "1" code bit, each said series of three code bits defining a predetermined one of four code words, the current and previous said code word determining whether a data bit of a first polarity or a data bit of a second polarity is generated by said decoding means; and means for outputting each said decoded data bit.

Claim 23

In a system for storing binary bode bits stored on a medium as a series of signal transitions, an apparatus for decoding binary data from said signal transitions comprising: means for detecting each said signal transition on a selected segment of said medium; means for generating a periodic clock signal as a function of the occurrence of said signal transitions; means responsive to said signal transitions for detecting a synchronization signal; means for converting each series of three code bits defined with respect to said synchronization signal into a predetermined data bit, wherein a "1" code bit signifies a signal transition and a "0" code bit signifies the absence of a signal transition when said clock signal indicates a signal transition clock time, and wherein 2, 4, 6, or 8 "0" code bits exist between each "1" code bit, each said series of three code bits defining a predetermined one of four code words, the current and previous said code word determining whether a data bit of a first polarity or a data bit of a second polarity is generated by said decoding means; and means for outputting each said decoded data bit.

Claim 24

A state machine for encoding a series of input binary bit, with each input bit being converted into a 3-bit output code, comprising: a memory for storing five states for producing a 3-bit code in response to one of said binary bits, each state changing (C) or not changing (N) the polarity of a previous output bit, with a state I(NNC), state II(NNN), state III(NCN), state IV(NNN) and state V(CNN); means for sequencing through said states based on a present state and a next input bit such that for present state I, a next input 0 causes a transition to state II and a next input 1 causes a transition back to state I, for present state II, a next input 0 causes a transition to state III and a next input 1 causes a transition to state IV, for present state III, a next input 0 causes a transition back to state III and a next input 1 causes a transition to state IV, for present state IV, a next input 0 causes a transition to state V and a next input 1 causes a transition to state I, for present state V, a next input 0 causes a transition back to state V and a next input 1 causes a transition to state I.

Claim 25

A state machine for encoding a series of input binary bit, with each input bit being converted into a 3-bit output code, comprising: a memory for storing five states for producing a 3-bit code in response to one of said binary bits, each state changing (C) or not changing (N) the polarity of a previous output bit, with a state I(NNC), state II(NNN), state III(NCN), state IV(NNN) and state V(CNN); means for sequencing through said states based on a present state and a next input bit such that for present state I, a next input 0 causes a transition to state II and a next input 1 causes a transition back to state I, for present state II, a next input 0 causes a transition to state III and a next input 1 causes a transition to state IV, for present state III, a next input 0 causes a transition back to state III and a next input 1 causes a transition to state IV, for present state IV, a next input 0 causes a transition to state V and a next input 1 causes a transition to state I, for present state V, a next input 0 causes a transition back to state V and a next input 1 causes a transition to state I.

Claim 26

The state machine of claim 20 further comprising a memory element for storing a synchronization state for generating a synchronization pattern; and means for selectively transitioning to said synchronization state between any two of said states.

Claim 27

The state machine of claim 20 wherein said state machine is polarized with each of said states including two polarized states (A and B) so that an N (not changing) and a C (changing) are a 1 in one polarization and a 0 in the other, giving states of: state IA (001), state IB (110), state IIA (111), state IIB (000), state IIIA (100), state IIIB (011), state IVA (000), state IVB (111), and state VA (111), state VB (000), wherein the transistions back to the same state are to the opposite polarity of that state.

Claim 28

The state machine of claim 22 wherein said states are modified to remove every odd 1 appearing in possible output sequences of said code bits for use with a laser which will produce a pit for each 1, each pit being large enough to be read back as 3 ones, such that the states become: state IA (000), state IB (100), state IIA (101), state IIB (000), state IIIA (000), state IIIB (001), state IVA (000), state IVB (010), and state VA (010), state VB (000).

Claim 29

The state machine of claim 22 further comprising means for sequencing said state machine to recreate said series of input binary bits upon the reading of a code corresponding to said states.

Claim 30

A state machine for encoding a series of input binary bits, with each bit being converted to a 3-bit output for writing onto an optical media such that each "1" corresponds to a laser being turned on, comprising: a memory for storing states with said 3-bit codes, said states being state IA (000), state IB (100), state IIA (101), state IIB (000), state IIIA (000), state IIIB (001), state IVA (000), state IVB (010), and state VA (010), state VB (000); and means for sequencing through said states based on a present state and a next input bit such that present state IA, next input 0 goes to state IIA, 1 goes to state IB, present state IB, next input 0 goes to state IIB, 1 goes to state IA, present state IIA, next input 0 goes to state IIIA, 1 goes to state VA, present state IIB, next input 0 goes to state IIIB, 1 goes to state VB, present state IIIA, next input 0 goes to state IIIB, 1 goes to state IVA, present state IIIB, next input 0 goes to state IIIA, 1 goes to state IVB, present state IVA, next input 0 goes to state VA, 1 goes to state IA, present state IVB, next input 0 goes to state VB, 1 goes to state IB, present state VA, next input 0 goes to state VB, 1 goes to IB, present state VB, next input 0 goes to state VA, 1 goes to IA.

Claim 31

A state machine for encoding a series of input binary bits, with each bit being converted to a 3-bit output for writing onto an optical media such that each "1" corresponds to a laser being turned on, comprising: a memory for storing states with said 3-bit codes, said states being state IA (000), state IB (100), state IIA (101), state IIB (000), state IIIA (000), state IIIB (001), state IVA (000), state IVB (010), and state VA (010), state VB (000); and means for sequencing through said states based on a present state and a next input bit such that present state IA, next input 0 goes to state IIA, 1 goes to state IB, present state IB, next input 0 goes to state IIB, 1 goes to state IA, present state IIA, next input 0 goes to state IIIA, 1 goes to state VA, present state IIB, next input 0 goes to state IIIB, 1 goes to state VB, present state IIIA, next input 0 goes to state IIIB, 1 goes to state IVA, present state IIIB, next input 0 goes to state IIIA, 1 goes to state IVB, present state IVA, next input 0 goes to state VA, 1 goes to state IA, present state IVB, next input 0 goes to state VB, 1 goes to state IB, present state VA, next input 0 goes to state VB, 1 goes to IB, present state VB, next input 0 goes to state VA, 1 goes to IA.

Claim 32

The state machine of claim 25 further comprising a synchronization state between two of said states for producing a synchronization pattern.

Claim 33

A state machine for decoding a series of 3-bit corresponding to different states to produce an output binary bit stream, comprising: means for recognizing codes corresponding to state IA (001), state IB (110), state IIA (111), state IIB (000), state IIIA (100), state IIIB (011), state IVA (000), state IVB (111), state VA (111), state VB (000); and means for producing output bits upon transitions between states such that states IA to IB and IB to 1A produces 1, states IA to IIA and IB to IIB produces 0, states IIA to VA and IIB to VB produces 1, states IIA to IIIA and IIB to IIIB produces 0, states IIIA to IVA and IIIB to IVB produces 1, states IIIA to IIIB and IIIB to IIIA produces 0, states IVA to IA and IVB to IB produces 1, states IVA to VA and IVB to VB produces 0, states VA to IB and VB to IA produce 1, and states VA to VB and VB to VA produces 0.

Claim 34

A state machine for decoding a series of 3-bit corresponding to different states to produce an output binary bit stream, comprising: means for recognizing codes corresponding to state IA (001), state IB (110), state IIA (111), state IIB (000), state IIIA (100), state IIIB (011), state IVA (000), state IVB (111), state VA (111), state VB (000); and means for producing output bits upon transitions between states such that states IA to IB and IB to 1A produces 1, states IA to IIA and IB to IIB produces 0, states IIA to VA and IIB to VB produces 1, states IIA to IIIA and IIB to IIIB produces 0, states IIIA to IVA and IIIB to IVB produces 1, states IIIA to IIIB and IIIB to IIIA produces 0, states IVA to IA and IVB to IB produces 1, states IVA to VA and IVB to VB produces 0, states VA to IB and VB to IA produce 1, and states VA to VB and VB to VA produces 0.

Claim 35

The state machine of claim 27 further comprising means for recognizing a synchronization code corresponding to a synchronization state between a specified two of said states.