US5171701A
Expired / Lapsed
US
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Method of manufacturing master-slice semiconductor integrated circuits
Assignee: Toshiba Corp
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Filing: 1991-07-12
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Granted: 1992-12-15
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Expires: 2011-07-12
Abstract
Abstract A method for forming in a short time master-slice integrated circuits of high reliability, which circuits comprise diffusion layers and polysilicon layers which form transistor elements, and a plurality of metal wiring layers formed for realizing desired circuits, with insulating layers interposed between every adjacent two of the wiring layers. The methods comprises a first wiring process in which a master slice is provided by forming a predetermined number of metal layers in a wafer, and a second wiring process in which further metal wiring layers, to be customized so as to have logical functions required by a user, are formed on the first-mentioned metal wiring layers. The inner-most metal wiring layer of all the metal layers is used as wide power source line which is almost free from electro or stress migration.
Inventors
- 👤 Masato Nagamatsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:39
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10W20/49; Y; Y10; Y10S; Y10S257/00; Y10S257/909
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
134 words
A method of manufacturing master-slice semiconductor integrated circuits to provide customized circuits, in which diffusion layers and gate electrodes, which form transistor elements, are preformed in and on a semiconductor wafer, and in which a plurality of metal wiring layers and interposed insulating layers are also preformed on the semiconductor wafer, the method comprising: a first wiring process to form a lowermost layer of the metal wiring layers together with the transistor elements on the wafer, said lowermost layer serving as a reinforcing layer for power source wiring to avoid electro migration and stress migration typically occurring on power source lines; and a second wiring process for customization to obtain a particular logic function required by a user by forming metal wiring layers above the metal wiring layer formed in said first wiring process.
Claim 2
Independent Claim
134 words
A method of manufacturing master-slice semiconductor integrated circuits to provide customized circuits, in which diffusion layers and gate electrodes, which form transistor elements, are preformed in and on a semiconductor wafer, and in which a plurality of metal wiring layers and interposed insulating layers are also preformed on the semiconductor wafer, the method comprising: a first wiring process to form a lowermost layer of the metal wiring layers together with the transistor elements on the wafer, said lowermost layer serving as a reinforcing layer for power source wiring to avoid electro migration and stress migration typically occurring on power source lines; and a second wiring process for customization to obtain a particular logic function required by a user by forming metal wiring layers above the metal wiring layer formed in said first wiring process.
Claim 3
Dependent Claim
27 words
The method of manufacturing master-slice semiconductor integrated circuits according to claim 1, wherein said reinforcing layer for the power source wiring is formed between the transistor elements.
Claim 4
Dependent Claim
32 words
The method of manufacturing master-slice semiconductor integrated circuits according to claim 1, wherein said reinforcing layer for the power source wiring is a broad power line surrounding each of the transistor elements.
Claim 5
Dependent Claim
34 words
The method of manufacturing master-slice semiconductor integrated circuits according to claim 1, wherein in the first wiring process, that partial wiring is preformed between some of the transistor elements which is not largely changed.
Claim 6
Dependent Claim
26 words
The method of manufacturing master-slice semiconductor integrated circuits according to claim 4, wherein the first wiring process includes the step of forming the power source line.
Claim 7
Dependent Claim
28 words
The method of manufacturing master-slice semiconductor integrated circuits according to claim 4, wherein the partial wiring defines a macro cell comprising a memory and a peripheral circuit thereof.
Claim 8
Independent Claim
159 words
A method of manufacturing master-slice semiconductor integrated circuits to provide customized circuits, in which diffusion layers and gate electrodes, which form transistor elements, are preformed in and on a semiconductor wafer, and in which a plurality of metal wiring layers and interposed insulating layers are also preformed on the semiconductor wafer, the method comprising: a first wiring process for arranging the transistor elements of a first electric conductivity type in a first line and the transistor elements of a second electric conductivity type in a second line and for forming a reinforcing layer only for the power source wiring as a master line between the first and second lines so as to avoid electro migration and stress migration typically occurring on power source lines; and a second wiring process for achieving customization to provide a logic function required by a user by forming the metal wiring layers located above a metal wiring layer formed by said first wiring process.
Claim 9
Independent Claim
159 words
A method of manufacturing master-slice semiconductor integrated circuits to provide customized circuits, in which diffusion layers and gate electrodes, which form transistor elements, are preformed in and on a semiconductor wafer, and in which a plurality of metal wiring layers and interposed insulating layers are also preformed on the semiconductor wafer, the method comprising: a first wiring process for arranging the transistor elements of a first electric conductivity type in a first line and the transistor elements of a second electric conductivity type in a second line and for forming a reinforcing layer only for the power source wiring as a master line between the first and second lines so as to avoid electro migration and stress migration typically occurring on power source lines; and a second wiring process for achieving customization to provide a logic function required by a user by forming the metal wiring layers located above a metal wiring layer formed by said first wiring process.
Claim 10
Dependent Claim
34 words
The method of manufacturing master-slice semiconductor integrated circuits according to claim 7, wherein in the first wiring process, that partial wiring is preformed between some of the transistor elements which is not largely changed.
Claim 11
Dependent Claim
28 words
The method of manufacturing master-slice semiconductor integrated circuits according to claim 8, wherein the partial wiring defines a macro cell comprising a memory and a peripheral circuit thereof.
Claim 12
Dependent Claim
29 words
The method of manufacturing master-slice semiconductor integrated circuits according to claim 7, wherein said reinforcing layer for the power source wiring comprises two wiring systems for supplying two voltages.
Claim 13
Dependent Claim
30 words
The method of manufacturing master-slice semiconductor integrated circuits according to claim 7, wherein said reinforcing layer for the power source wiring is formed to surround each of the transistor elements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-15 | 1996-06-15 | 1996-12-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-15 | 2000-06-15 | 2000-12-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-15 | 2004-06-15 | 2004-12-15 | $7700.00 | Window Closed / Lapsed |