Subtitling apparatus with memory control codes interspersed with graphic data

Claim 1

An apparatus for selecting a video signal from a plurality of video signals previously stored in a memory and for superimposing the selected video signal on another video signal, comprising: (a) said memory having stored therein at least two video signals to be superimposed on said another video signal, each video signal to be superimposed including predetermined control codes which have been stored every 2 n addresses (n is a positive integer) in said memory; (b) a code detecting circuit for detecting a type of said predetermined control codes which indicate a head address of a video signal to be superimposed read out from said memory; (c) a first memory address generating circuit for generating lower n bits of an address signal to be applied to said memory; (d) second memory address generating circuit for generating upper bits, other than the lower n bits, of said address signal to be applied to said memory; and (e) a memory address control circuit for controlling the first and second memory address generating circuits such that video signals stored in the memory are sequentially read out from said memory in response to said address signal, and when a video signal to be superimposed on said another video signal is selected, said first memory address generating circuit is controlled so that values of the lower n bits of said address signal are fixed to an address at which said predetermined control codes are stored, and said second memory address generating circuit is controlled so that said upper bits of said address signal are increased or decreased, thereby reading out only said predetermined control codes from said memory and repeatedly increasing or decreasing the upper bits of said address signal until said selected video signal to be superimposed on said another video signal is detected based on a result of said detection by said code detecting circuit.

Claim 2

An apparatus for selecting a video signal from a plurality of video signals previously stored in a memory and for superimposing the selected video signal on another video signal, comprising: (a) said memory having stored therein at least two video signals to be superimposed on said another video signal, each video signal to be superimposed including predetermined control codes which have been stored every 2 n addresses (n is a positive integer) in said memory; (b) a code detecting circuit for detecting a type of said predetermined control codes which indicate a head address of a video signal to be superimposed read out from said memory; (c) a first memory address generating circuit for generating lower n bits of an address signal to be applied to said memory; (d) second memory address generating circuit for generating upper bits, other than the lower n bits, of said address signal to be applied to said memory; and (e) a memory address control circuit for controlling the first and second memory address generating circuits such that video signals stored in the memory are sequentially read out from said memory in response to said address signal, and when a video signal to be superimposed on said another video signal is selected, said first memory address generating circuit is controlled so that values of the lower n bits of said address signal are fixed to an address at which said predetermined control codes are stored, and said second memory address generating circuit is controlled so that said upper bits of said address signal are increased or decreased, thereby reading out only said predetermined control codes from said memory and repeatedly increasing or decreasing the upper bits of said address signal until said selected video signal to be superimposed on said another video signal is detected based on a result of said detection by said code detecting circuit.