US5166553A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current mirror circuit employing depletion mode FETs
Assignee: Hitachi Ltd
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Filing: 1989-06-12
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Granted: 1992-11-24
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Expires: 2009-06-12
Abstract
Abstract A semiconductor circuit including first and second FET's for delivering an output signal without being affected by a change in threshold voltage of the FET's is disclosed. According to one practical form of the semiconductor circuit, the drain-source current path of an additional FET whose gate and source are shorted to each other, is connected in parallel to the drain-source current path of the first FET whose gate and drain are shorted to each other, to make the voltage-current characteristic of the second FET agree with that of the parallel combination of the first and additional FET's. According to another practical form of the semiconductor circuit, a voltage dividing circuit is connected in parallel to the drain-source current path of the first FET, and a divided output voltage from the voltage dividing circuit is applied between the gate and source of each of the first and second FET's.
Inventors
- 👤 Nobuo Kotera
- 👤 Kiichi Yamashita
- 👤 Hirotoshi Tanaka
- 👤 Satoshi Tanaka
- 👤 Yasushi Hatta
- 👤 Minoru Nagata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:17
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/14; H03K17/145; G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/262
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
221 words
A semiconductor circuit comprising first, second and third field effect transistors each one having a gate, source and drain and having a threshold of a same voltage value, the gate and drain of the first field effect transistor being electrically connected to each other, the gate and source of the second field effect transistor being electrically connected to each other, the sources of the first and second field effect transistors being connected to each other, the gate and the drain of the first field effect transistor and the drain of the second field effect transistor being connected to one of the gate and the source of the third field effect transistor, the first field effect transistor including a drain-source current path connected in parallel to a drain-source current path included in the second field effect transistor, and the gate of the third field effect transistor being applied with an input and one of the source and drain thereof providing an output, whereby a voltage versus current characteristic corresponding to the parallel connection of the drain-source current paths of the first and second field effect transistors is in agreement with a gate-source voltage versus drain-source current characteristic corresponding to that of the third field effect transistor independently of a change in threshold voltage of the first, second and third field effect transistors.
Claim 2
Dependent Claim
221 words
A semiconductor circuit comprising first, second and third field effect transistors each one having a gate, source and drain and having a threshold of a same voltage value, the gate and drain of the first field effect transistor being electrically connected to each other, the gate and source of the second field effect transistor being electrically connected to each other, the sources of the first and second field effect transistors being connected to each other, the gate and the drain of the first field effect transistor and the drain of the second field effect transistor being connected to one of the gate and the source of the third field effect transistor, the first field effect transistor including a drain-source current path connected in parallel to a drain-source current path included in the second field effect transistor, and the gate of the third field effect transistor being applied with an input and one of the source and drain thereof providing an output, whereby a voltage versus current characteristic corresponding to the parallel connection of the drain-source current paths of the first and second field effect transistors is in agreement with a gate-source voltage versus drain-source current characteristic corresponding to that of the third field effect transistor independently of a change in threshold voltage of the first, second and third field effect transistors.
Claim 3
Dependent Claim
24 words
A semiconductor circuit according to claim 1, wherein the first, second and third field effect transistors are formed on a single integration circuit chip.
Claim 4
Dependent Claim
22 words
A semiconductor circuit according to claim 2, wherein the first, second and third field effect transistors are N-channel, depletion-type field effect transistors.
Claim 5
Dependent Claim
122 words
A current mirror circuit comprising: an input node; an output node; a common node; and first, second and third field effect transistors each one having a gate, source and drain and having a threshold of a same voltage value, the input node being electrically connected to the gate and drain of the first field effect transistor, the drain of the second field effect transistor and the gate of the third field effect transistor, the output node being electrically connected to the drain of the third field effect transistor, the common node being electrically connected to the source of the first field effect transistor, the gate and source of the second field effect transistor and the source of the third field effect transistor.
Claim 6
Dependent Claim
122 words
A current mirror circuit comprising: an input node; an output node; a common node; and first, second and third field effect transistors each one having a gate, source and drain and having a threshold of a same voltage value, the input node being electrically connected to the gate and drain of the first field effect transistor, the drain of the second field effect transistor and the gate of the third field effect transistor, the output node being electrically connected to the drain of the third field effect transistor, the common node being electrically connected to the source of the first field effect transistor, the gate and source of the second field effect transistor and the source of the third field effect transistor.
Claim 7
Dependent Claim
66 words
A current mirror circuit according to claim 4, further comprising a level shift circuit, one end of the level shift circuit being connected to the gate and drain of the first field effect transistor and the gate of the third field effect transistor, the other end of the level shift circuit being connected to the drain of the second field effect transistor and the input node.
Claim 8
Dependent Claim
71 words
A current mirror circuit according to claim 5, further comprising a fourth field effect transistor, the gate of the fourth field effect transistor being connected to the input node and the other end of the level shift circuit, the source of the fourth field effect transistor being connected to the drain of the third field effect transistor, the drain of the fourth field effect transistor being connected to the output node.
Claim 9
Dependent Claim
28 words
A current mirror circuit according to claim 6, wherein at least the first, second, third and fourth field effect transistors are formed on a single integration circuit chip.
Claim 10
Dependent Claim
62 words
A current mirror circuit according to claim 6, wherein the first, second, third and fourth field effect transistors are N-channel, depletion-type field effect transistors, the first transistor is disposed to operate in the linear region of its corresponding current-voltage characteristic curve and the second, third and fourth transistors are disposed to operate in the saturation region of their respective current-voltage characteristic curve.
Claim 11
Dependent Claim
32 words
A current mirror circuit according to claim 8, wherein the level shift circuit is comprised of one of a resistor, Schottky barrier diode and diode-connected field effect transistor or a combination thereof.
Claim 12
Dependent Claim
27 words
A current mirror circuit according to claim 5, wherein at least the first, second and third field effect transistors are formed on a single integration circuit chip.
Claim 13
Dependent Claim
32 words
A current mirror circuit according to claim 10, wherein the level shift circuit is comprised of one of a resistor, Schottky barrier diode and diode-connected field effect transistor or a combination thereof.
Claim 14
Dependent Claim
26 words
A current mirror circuit according to claim 4, wherein a resistor is connected between the source of the third field effect transistor and the common node.
Claim 15
Dependent Claim
27 words
A current mirror circuit according to claim 12, wherein at least the first, second and third field effect transistors are formed on a single integration circuit chip.
Claim 16
Dependent Claim
27 words
A current mirror circuit according to claim 4, wherein at least the first, second and third field effect transistors are formed on a single integration circuit chip.
Claim 17
Dependent Claim
49 words
A current mirror circuit according to claim 4, wherein the first field effect transistor is disposed to operate in the linear region of its corresponding current-voltage characteristic curve and the second and third field transistors are disposed to operate in the saturation region of their respective current-voltage characteristic curve.
Claim 18
Dependent Claim
22 words
A current mirror circuit according to claim 15, wherein the first, second and third field effect transistors are N-channel, depletion-type-field effect transistors.
Claim 19
Dependent Claim
27 words
A current mirror circuit according to claim 16, wherein at least the first, second and third field effect transistors are formed on a single integration circuit chip.
Claim 20
Dependent Claim
26 words
A current mirror circuit according to claim 17, wherein a resistor is connected between the source of the third field effect transistor and the common node.
Claim 21
Dependent Claim
150 words
A current mirror circuit comprising: an input node; an output node; a common node; and first, second, third and fourth field effect transistors each one having a gate, source and drain and having a threshold of a same voltage value, the input node being electrically connected to the drain of the first field effect transistor and the gate of the fourth field effect transistor, the output node being electrically connected to the drain of the fourth field effect transistor, the common node being electrically connected to the source of each of the first, second and third field effect transistors and connected to the gate of the third field effect transistor, and the gate of the first field effect transistor being electrically connected to the gate and drain of the second field effect transistor, the drain of the third field effect transistor and the source of the fourth field effect transistor.
Claim 22
Dependent Claim
150 words
A current mirror circuit comprising: an input node; an output node; a common node; and first, second, third and fourth field effect transistors each one having a gate, source and drain and having a threshold of a same voltage value, the input node being electrically connected to the drain of the first field effect transistor and the gate of the fourth field effect transistor, the output node being electrically connected to the drain of the fourth field effect transistor, the common node being electrically connected to the source of each of the first, second and third field effect transistors and connected to the gate of the third field effect transistor, and the gate of the first field effect transistor being electrically connected to the gate and drain of the second field effect transistor, the drain of the third field effect transistor and the source of the fourth field effect transistor.
Claim 23
Dependent Claim
26 words
A current mirror circuit according to claim 19, wherein the first, second, third and fourth field effect transistors are formed on a single integration circuit chip.
Claim 24
Dependent Claim
62 words
A current mirror circuit according to claim 19, wherein the first, second, third and fourth field effect transistors are N-channel, depletion-type field effect transistors, the first, third and fourth transistors are disposed to operate in the saturation region of their respective current-voltage characteristic curve and the second transistor is disposed to operate in its linear region of its corresponding current-voltage characteristic curve.
References Cited (Backward Citations)
EP0203384A2
Cited
US4926071A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-24 | 1996-05-25 | 1996-11-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-24 | 2000-05-25 | 2000-11-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-24 | 2004-05-25 | 2004-11-24 | $7700.00 | Window Closed / Lapsed |