Method of manufacturing semiconductor device contact vias in layers comprising silicon nitride and glass

Claim 1

A method of manufacturing a semiconductor device, comprising the steps of: forming a first insulating layer, having at a surface thereof a concave area to which a contact hole is to be formed and a convex area, on a semiconductor substrate; forming a high resistance portion comprising polycrystalline silicon, on said convex area; forming a protection layer comprising SiN on said first insulating layer and said high resistance portion; removing a portion of said formed protection protection layer at said concave area such that said removed portion includes an area to form said contact hole and is larger than said area to form said contact hole before forming said contact hole; forming a second insulating layer including at least boron as an impurity on said protection layer and said first insulating layer; forming said contact hole at said concave area from said second insulating layer to a surface of said semiconductor substrate by means of an etching technique; and forming a metal wiring in said contact hole and on said second insulating layer.

Claim 2

A method of manufacturing a semiconductor device, comprising the steps of: forming a first insulating layer, having at a surface thereof a concave area to which a contact hole is to be formed and a convex area, on a semiconductor substrate; forming a high resistance portion comprising polycrystalline silicon, on said convex area; forming a protection layer comprising SiN on said first insulating layer and said high resistance portion; removing a portion of said formed protection protection layer at said concave area such that said removed portion includes an area to form said contact hole and is larger than said area to form said contact hole before forming said contact hole; forming a second insulating layer including at least boron as an impurity on said protection layer and said first insulating layer; forming said contact hole at said concave area from said second insulating layer to a surface of said semiconductor substrate by means of an etching technique; and forming a metal wiring in said contact hole and on said second insulating layer.

Claim 5

A method of manufacturing a semiconductor device comprising the steps of: forming a first insulating layer, having at a surface thereof a concave area to which a contact hole is to be formed and a convex area, on a semiconductor substrate; forming a high resistance portion comprising polycrystalline silicon, on said convex area; forming an anti-etching barrier layer on said first insulating layer and said high resistance portion; forming a protection layer comprising SiN on said anti-etching barrier layer; forming a second insulating layer including at least boron as an impurity on said protection layer; forming said contact hole at said concave area from said second insulating layer to a surface of said semiconductor substrate by means of an etching technique such that said high resistance portion is prevented by said anti-etching barrier layer from being exposed to an etching condition; and forming a metal wiring in said contact hole and on said second insulating layer.

Claim 6

A method of manufacturing a semiconductor device comprising the steps of: forming a first insulating layer, having at a surface thereof a concave area to which a contact hole is to be formed and a convex area, on a semiconductor substrate; forming a high resistance portion comprising polycrystalline silicon, on said convex area; forming an anti-etching barrier layer on said first insulating layer and said high resistance portion; forming a protection layer comprising SiN on said anti-etching barrier layer; forming a second insulating layer including at least boron as an impurity on said protection layer; forming said contact hole at said concave area from said second insulating layer to a surface of said semiconductor substrate by means of an etching technique such that said high resistance portion is prevented by said anti-etching barrier layer from being exposed to an etching condition; and forming a metal wiring in said contact hole and on said second insulating layer.

Claim 9

A method of manufacturing a semiconductor device, comprising the steps of: forming a first insulating layer, having at a surface thereof a concave area to which a contact hole is to be formed and a convex area, on a semiconductor substrate; forming a high resistance portion comprising polycrystalline silicon, on said convex area; forming a protection layer comprising SiN on said first insulating layer and said high resistance portion; forming an insulating interlayer which does not include boron, on said protection layer; forming a second insulating layer including at least boron as an impurity on said insulating interlayer such that said second insulating layer does not have contact with said protection layer by the existence of said insulating interlayer therebetween; forming said contact hole at said concave area from said second insulating layer to a surface of said semiconductor substrate by means of an etching technique; and forming a metal wiring in said contact hole and on said second insulating layer.

Claim 10

A method of manufacturing a semiconductor device, comprising the steps of: forming a first insulating layer, having at a surface thereof a concave area to which a contact hole is to be formed and a convex area, on a semiconductor substrate; forming a high resistance portion comprising polycrystalline silicon, on said convex area; forming a protection layer comprising SiN on said first insulating layer and said high resistance portion; forming an insulating interlayer which does not include boron, on said protection layer; forming a second insulating layer including at least boron as an impurity on said insulating interlayer such that said second insulating layer does not have contact with said protection layer by the existence of said insulating interlayer therebetween; forming said contact hole at said concave area from said second insulating layer to a surface of said semiconductor substrate by means of an etching technique; and forming a metal wiring in said contact hole and on said second insulating layer.

Claim 13

A method of manufacturing a semiconductor device, comprising the steps of: forming a first insulating layer, having at a surface thereof a concave area to which a contact hole is to be formed and a convex area, on a semiconductor substrate; forming a high resistance portion comprising polycrystalline silicon, on said convex area; forming an anti-etching barrier layer on said first insulating layer and said high resistance portion; forming a protection layer comprising SiN on said anti-etching barrier layer; removing a portion of said formed protection layer at said concave area such that said removed portion includes an area to form said contact hole and is larger than said area to form said contact hole before forming said contact hole; forming an insulating interlayer which does not include boron, on said protection layer and said anti-etching barrier layer; forming a second insulating layer including at least boron as an impurity on said insulating interlayer such that said second insulating layer does not have contact with said protection layer by the existence of said insulating interlayer therebetween; forming said contact hole at said concave area from said second insulating layer to a surface of said semiconductor substrate by means of an etching technique such that said high resistance portion is prevented by said anti-etching barrier layer from being exposed to an etching condition; and forming a metal wiring in said contact hole and on said second insulating layer.

Claim 14

A method of manufacturing a semiconductor device, comprising the steps of: forming a first insulating layer, having at a surface thereof a concave area to which a contact hole is to be formed and a convex area, on a semiconductor substrate; forming a high resistance portion comprising polycrystalline silicon, on said convex area; forming an anti-etching barrier layer on said first insulating layer and said high resistance portion; forming a protection layer comprising SiN on said anti-etching barrier layer; removing a portion of said formed protection layer at said concave area such that said removed portion includes an area to form said contact hole and is larger than said area to form said contact hole before forming said contact hole; forming an insulating interlayer which does not include boron, on said protection layer and said anti-etching barrier layer; forming a second insulating layer including at least boron as an impurity on said insulating interlayer such that said second insulating layer does not have contact with said protection layer by the existence of said insulating interlayer therebetween; forming said contact hole at said concave area from said second insulating layer to a surface of said semiconductor substrate by means of an etching technique such that said high resistance portion is prevented by said anti-etching barrier layer from being exposed to an etching condition; and forming a metal wiring in said contact hole and on said second insulating layer.