US5165036A — Parallel processing development system with debug…

Claim 1

Independent Claim 122 words

A parallel processor development system comprising: parallel processing means including a plurality of function portions and ports provided at predetermined points in said plurality of function portions for processing data packets, controlling means for controlling said parallel processing means and supplying data packets to be processed by said parallel processing means, inputting means for storing the data packets supplied by said controlling means and inputting said data packets to said parallel processing means at a predetermined time interval, a plurality of tracing means connected to a plurality of said ports of said parallel processing means for storing data packets taken from said plurality of said ports together with common timing information, and displaying means for displaying storage contents of said tracing means.

Claim 2

Dependent Claim 122 words

A parallel processor development system comprising: parallel processing means including a plurality of function portions and ports provided at predetermined points in said plurality of function portions for processing data packets, controlling means for controlling said parallel processing means and supplying data packets to be processed by said parallel processing means, inputting means for storing the data packets supplied by said controlling means and inputting said data packets to said parallel processing means at a predetermined time interval, a plurality of tracing means connected to a plurality of said ports of said parallel processing means for storing data packets taken from said plurality of said ports together with common timing information, and displaying means for displaying storage contents of said tracing means.

Claim 3

Dependent Claim 19 words

A parallel processor developing system according to claim 1, wherein said parallel processing means comprises more than two processors.

Claim 4

Dependent Claim 25 words

A parallel processor developing system according to claim 2, wherein each said processor is a data driven type processor for executing a data flow program.

Claim 5

Dependent Claim 69 words

A parallel processor developing system according to claim 3, wherein said data driven type processor comprises: program storing means for storing a data flow program and outputting a data packet based on said data flow program, paired data generating means for detecting two data packets to be paired, and operation processing means for subjecting a data packet outputted form said paired data generating means to a specified processing operation.

Claim 6

Dependent Claim 50 words

A parallel processor developing system according to claim 1, wherein said inputting means comprises: first storing means for storing data packets supplied from said controlling means, and measuring means for inputting said data packets stored in said first storing means to said parallel processing means at a predetermined time interval.

Claim 7

Dependent Claim 27 words

A parallel processor developing system according to claim 5, wherein said inputting means further comprising microprocessor means for controlling said first storing means and said measuring means.

Claim 8

Dependent Claim 62 words

A parallel processor developing system according to claim 6, wherein said first storing means comprises: first memory means for storing a plurality of data packets, writing addressing means for addressing to write said data packets supplied from said controlling means into said first memory means, and reading addressing means for addressing to read out a data packet stored in said memory means.

Claim 9

Dependent Claim 58 words

A parallel processor developing system according to claim 7, wherein said measuring means comprises: output port means for applying said data packet read out from said first storing means to said parallel processing means, and output port controlling means for driving said output port means based on information regarding said predetermined time interval supplied from said microprocessor means.

Claim 10

Dependent Claim 59 words

A parallel processor developing system according to claim 1, wherein each said tracing means comprises: timer means for generating said common timing information, second storing means for storing said data packets taken from any of said ports together with said common timing information, and read/write controlling means for controlling reading operation and writing operation of said second storing means.

Claim 11

Dependent Claim 68 words

A parallel processor developing system according to claim 9, wherein said second storing means comprises: third means for storing a plurality of data packets together with said common timing information, addressing means for addressing said memory means, and breakpoint means having a present breakpoint value and which stops an operation of said tracing means upon detection of a data packet having the same value as the breakpoint value.

Claim 12

Dependent Claim 50 words

A parallel processor developing system according to claim 1, wherein said displaying means has a function of displaying data packets processed in said parallel processing means in a predetermined order as said data packets are processed and a function of comparing said data packets with a program to be executed.

Claim 13

Dependent Claim 47 words

A parallel processor developing system according to claim 11, wherein said displaying means has a function of collecting a plurality of trace results from said tracing means, storing said trace results, arranging the stored trace results into a data flow graph and displaying the data flow graph.

Claim 14

Dependent Claim 189 words

A debug device for a data driven type processor including program storing means for storing a data flow program and outputting a data packet based on said data flow program, paired data generating means for detecting two data packets to be paired and operation processing means for subjecting a data packet outputted from said paired data generating means to a specified operation processing, comprising: debug information storing means for storing debug information regarding said data flow program, operation packet observing means for observing a data packet which has been subjected to an operation processing in said operation processing means, queue packet observing means for observing data packets queuing data packets to be paired in said paired data generating means, and execution state displaying means for schematically displaying an execution state of said data driven type processor based on said debug information stored in said debug information storing means and observed information obtained from said operation packet observing means and said queue packet observing means, said execution state observing means being operatively connected to said queue packet observing means, said operation packet observing means and said debug information storing means.

Claim 15

Dependent Claim 189 words

A debug device for a data driven type processor including program storing means for storing a data flow program and outputting a data packet based on said data flow program, paired data generating means for detecting two data packets to be paired and operation processing means for subjecting a data packet outputted from said paired data generating means to a specified operation processing, comprising: debug information storing means for storing debug information regarding said data flow program, operation packet observing means for observing a data packet which has been subjected to an operation processing in said operation processing means, queue packet observing means for observing data packets queuing data packets to be paired in said paired data generating means, and execution state displaying means for schematically displaying an execution state of said data driven type processor based on said debug information stored in said debug information storing means and observed information obtained from said operation packet observing means and said queue packet observing means, said execution state observing means being operatively connected to said queue packet observing means, said operation packet observing means and said debug information storing means.

Claim 16

Dependent Claim 47 words

A parallel processor developing system according to claim 13, wherein said debug information includes information regarding a corresponding relation between the source program and a data flow program obtained by developing the source program and information regarding said data flow program stored in said program storing means.

Claim 17

Dependent Claim 41 words

A parallel processor developing system according to claim 14, wherein said execution state displaying means displays a data flow graph based on a corresponding relation between the source program and the data flow program stored in said debug information storing means.

Claim 18

Dependent Claim 38 words

A parallel processor developing system according to claim 15, wherein said operation packet observing means stores destination information, operation result information and time information of all data packets to which operations are performed by said operation processing means.

Claim 19

Dependent Claim 41 words

A parallel processor developing system according to claim 16, wherein said execution state displaying means displays an execution state of said data driven type processor on said data flow graph based on said information stored in said operation packet observing means.

Claim 20

Dependent Claim 38 words

A parallel processor developing system according to claim 17, wherein said queue packet observing means stores destination information, data information and time information of data packets queuing data packets to be paired in said paired data generating means.

Claim 21

Dependent Claim 64 words

A parallel processor developing system according to claim 18, wherein said execution state displaying means displays an execution state of said data driven type processor and queuing states of the data packets in said paired data generating means on said data flow graph based on said information stored in said operation packet observing means and said information stored in said queue packet observing means.

Claim 22

Dependent Claim 171 words

A parallel processor developing system according to claim 13, wherein said program storing means stores a data flow program comprising a plurality of destination information and a plurality of instruction information, inputs a data packet including the destination information, the instruction information and data, reads the next destination information and instruction information from said data flow program in accordance with the destination information of the inputted data packet, and stores the destination information and the instruction information into said data packet and outputs the same, said paired data generating means queues said data packets outputted from said program storing means and stores one of data packets of the two data packets having the same destination information into the other data packet and outputs the other data packet, said operation processing means encodes the instruction information of the data packets outputted from said paired data generating means, performs a specified operation processing to one or two data of said data packets, stores the result in the data packet and outputs the same.

Claim 23

Independent Claim 84 words

A method of developing a parallel processor, comprising the steps of: supplying data packets to be processed by said parallel processor, storing said supplied data packets externally of said parallel processor, inputting said stored data packets into said parallel processor at a predetermined time interval, taking data packets from predetermined portions of said parallel processor and storing externally of said parallel processor the data packets together with information regarding said predetermined time interval, and displaying said data packets stored together with said time information.

Claim 24

Independent Claim 84 words

A method of developing a parallel processor, comprising the steps of: supplying data packets to be processed by said parallel processor, storing said supplied data packets externally of said parallel processor, inputting said stored data packets into said parallel processor at a predetermined time interval, taking data packets from predetermined portions of said parallel processor and storing externally of said parallel processor the data packets together with information regarding said predetermined time interval, and displaying said data packets stored together with said time information.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1995-11-17	1996-05-18	1996-11-17	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1999-11-17	2000-05-18	2000-11-17	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2003-11-17	2004-05-18	2004-11-17	$7700.00	Window Closed / Lapsed

Parallel processing development system with debugging device includes facilities for schematically displaying execution state of data driven type processor

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag