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Patent US5165025A successfully refreshed from Google Patents.
US5165025A
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US
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Interlacing the paths after a conditional branch like instruction
Assignee: Individual
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Filing: 1991-05-30
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Granted: 1992-11-17
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Expires: 2011-05-30
Abstract
Abstract By interlacing the two program paths after the test part of a conditional branch, both program paths are available (with minimal delay) from a simple instruction fetch mechanism. Further, the interlacing of program paths continues only until one path ends with an unconditional branch or return.
Inventors
- 👤 Stanley E. Lass
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 14:10
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3804
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
123 words
An improved instruction supplying mechanism for use in a high speed computer which includes a double word instruction fetch mechanism, supplies instructions sequentially, and accepts new addresses into the program counter, wherein the improvement for reducing conditional branch delays comprises: means to supply instructions from the odd address words in fetched double words in response to a condition true from a conditional branch like test, and means to supply instructions from the even address words in fetched double words in response to a condition false from a conditional branch like test, whereby a simple double word instruction fetch mechanism provides both paths after a conditional branch like test instruction and conventional unconditional branch and return instructions provide means to exit from interlaced execution.
Claim 2
Dependent Claim
123 words
An improved instruction supplying mechanism for use in a high speed computer which includes a double word instruction fetch mechanism, supplies instructions sequentially, and accepts new addresses into the program counter, wherein the improvement for reducing conditional branch delays comprises: means to supply instructions from the odd address words in fetched double words in response to a condition true from a conditional branch like test, and means to supply instructions from the even address words in fetched double words in response to a condition false from a conditional branch like test, whereby a simple double word instruction fetch mechanism provides both paths after a conditional branch like test instruction and conventional unconditional branch and return instructions provide means to exit from interlaced execution.
Claim 3
Dependent Claim
44 words
The improved instruction supplying mechanism of claim 1 further including means to detect during interlaced execution the end of interlacing and transition to sequential supplying of instructions, said means to detect is by detecting unconditional branch and return instructions in the not executing path.
Claim 4
Dependent Claim
41 words
The improved instruction supplying mechanism of claim 1 further including means to detect during interlaced execution the end of interlacing and transition to sequential supplying of instructions, said means to detect uses an encoded length of interlacing in condition test instructions.
Claim 5
Dependent Claim
164 words
An improved instruction supplying mechanism for use in a high speed computer which includes a double word instruction fetch mechanism, supplies instructions sequentially, and accepts new addresses into the program counter, wherein the improvement for reducing conditional branch delays and minimizing replication of instructions comprises: means to supply instructions from the odd address words in fetched double words in response to a condition true from a conditional branch like test and in response to an unconditional branch to interlaced instructions in which the branch target address is odd, and means to supply instructions from the even address words in fetched double words in response to a condition false from a conditional branch like test and in response to an unconditional branch to interlaced instructions in which the branch target address is even, whereby a simple double word instruction fetch mechanism provides both paths after a conditional branch like test instruction and conventional unconditional branch and return instructions provide means to exit from interlaced execution.
Claim 6
Dependent Claim
164 words
An improved instruction supplying mechanism for use in a high speed computer which includes a double word instruction fetch mechanism, supplies instructions sequentially, and accepts new addresses into the program counter, wherein the improvement for reducing conditional branch delays and minimizing replication of instructions comprises: means to supply instructions from the odd address words in fetched double words in response to a condition true from a conditional branch like test and in response to an unconditional branch to interlaced instructions in which the branch target address is odd, and means to supply instructions from the even address words in fetched double words in response to a condition false from a conditional branch like test and in response to an unconditional branch to interlaced instructions in which the branch target address is even, whereby a simple double word instruction fetch mechanism provides both paths after a conditional branch like test instruction and conventional unconditional branch and return instructions provide means to exit from interlaced execution.
Claim 7
Dependent Claim
44 words
The improved instruction supplying mechanism of claim 4 further including means to detect during interlaced execution the end of interlacing and transition to sequential supplying of instructions, said means to detect is by detecting unconditional branch and return instructions in the not executing path.
Claim 8
Dependent Claim
50 words
The improved instruction supplying mechanism of claim 4 further including means to detect during interlaced execution the end of interlacing and transition to sequential supplying of instructions, said means to detect uses an encoded length of interlacing in the instructions for condition test and in unconditional branch to interlaced instructions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-17 | 1996-05-18 | 1996-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-17 | 2000-05-18 | 2000-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-17 | 2004-05-18 | 2004-11-17 | $7700.00 | Window Closed / Lapsed |