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US5164943A
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Cyclic redundancy check circuit
Assignee: National Semiconductor Corp
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Filing: 1992-03-06
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Granted: 1992-11-17
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Expires: 2012-03-06
Abstract
Abstract A media access controller is provided by the present invention. A feature of the media access controller of the present invention is a content addressable memory architecture whereby address filtering is provided for filtering physical, group and broadcast addresses on an Ethernet network. Another feature of the present invention is an interface architecture capable of supporting external address filters which in turn are capable of supporting spanning tree and source routing algorithms. Still another feature of the present invention is a CRC checker having improved testability such that burdensome computations for input bit test patterns are no longer required. Still another feature of the present invention is a first-in, first-out memory register having validity bits associated with each stored data byte, such that data bytes may be indiscriminately stored, regardless of their validity, and invalid data bytes are discarded during retrieval of the stored data bytes.
Inventors
- 👤 Edwin Z. DeSouza
- 👤 Daniel J. Cimino
- 👤 Ramin Shirani
- 👤 Mark R. Waggoner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:02
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L49/00; H04L49/90; H04L49/901; G; G11; G11C; G11C15/00; G11C15/04; H04L12/46; H04L12/4604; H04L12/462; H04L12/4625; H04L45/00; H04L45/74; H04L45/745; H04L45/7453; H04L49/9057
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
74 words
An improvement in a cyclic redundancy check circuit, said cyclic redundancy check circuit having an input data signal and comprising a plurality of shift registers and exclusive-OR gates, including an input exclusive-OR gate, said improvement comprising: a plurality of AND gates operatively coupled to selectably cause the outputs of said exclusive-OR gates to follow active inputs thereto; and a multiplexer operatively coupled to allow said input data signal to bypass said input exclusive-OR gate.
Claim 2
Dependent Claim
74 words
An improvement in a cyclic redundancy check circuit, said cyclic redundancy check circuit having an input data signal and comprising a plurality of shift registers and exclusive-OR gates, including an input exclusive-OR gate, said improvement comprising: a plurality of AND gates operatively coupled to selectably cause the outputs of said exclusive-OR gates to follow active inputs thereto; and a multiplexer operatively coupled to allow said input data signal to bypass said input exclusive-OR gate.
Claim 3
Dependent Claim
379 words
A cyclic redundancy check circuit coupled to perform polynomial modulo two arithmetic upon binary numbers expressed in digital data signal form, said cyclic redundancy check circuit comprising: a plurality of serially coupled groups of serial shift registers, each of said groups of shift registers comprising a data input, a data output and a set signal input, wherein all of said set signal inputs are coupled together as a common set input to receive a common set signal; a plurality of exclusive-OR logic gates serially interconnected between said groups of shift registers, each of said logic gates comprising first and second inputs and an output, wherein the output of each logic gate is coupled respectively to a data input of one of said groups of shift registers and the corresponding first input of said logic gate is coupled to the data output of the preceding group of shift registers, and further wherein all of said second inputs of said logic gates are coupled together as a common XOR input to receive a common XOR input signal; an input exclusive-OR logic gate comprising a first and second input and an output, wherein said first input is coupled to said data output of the last group of said serially coupled groups of serial shift registers, and said second input is coupled to receive an input digital data signal; set signal generator means for generating said common set signal; XOR signal selector means for selecting a signal to be coupled to said common XOR input, said XOR signal selector means comprising first and second inputs and an output, said output coupled to said common XOR input, said first input coupled to said output of said input exclusive-OR logic gate, and said second input coupled to receive an input test signal; and input data signal selector means for selecting an input data signal to be coupled to the data input of the first group of said serially coupled groups of serial shift registers, said input data signal selector means comprising first and second inputs and an output, said output being coupled to said data input of said first group of shift registers, and said first and second inputs being coupled to said second input and said output of said input exclusive-OR logic gate, respectively.
Claim 4
Dependent Claim
379 words
A cyclic redundancy check circuit coupled to perform polynomial modulo two arithmetic upon binary numbers expressed in digital data signal form, said cyclic redundancy check circuit comprising: a plurality of serially coupled groups of serial shift registers, each of said groups of shift registers comprising a data input, a data output and a set signal input, wherein all of said set signal inputs are coupled together as a common set input to receive a common set signal; a plurality of exclusive-OR logic gates serially interconnected between said groups of shift registers, each of said logic gates comprising first and second inputs and an output, wherein the output of each logic gate is coupled respectively to a data input of one of said groups of shift registers and the corresponding first input of said logic gate is coupled to the data output of the preceding group of shift registers, and further wherein all of said second inputs of said logic gates are coupled together as a common XOR input to receive a common XOR input signal; an input exclusive-OR logic gate comprising a first and second input and an output, wherein said first input is coupled to said data output of the last group of said serially coupled groups of serial shift registers, and said second input is coupled to receive an input digital data signal; set signal generator means for generating said common set signal; XOR signal selector means for selecting a signal to be coupled to said common XOR input, said XOR signal selector means comprising first and second inputs and an output, said output coupled to said common XOR input, said first input coupled to said output of said input exclusive-OR logic gate, and said second input coupled to receive an input test signal; and input data signal selector means for selecting an input data signal to be coupled to the data input of the first group of said serially coupled groups of serial shift registers, said input data signal selector means comprising first and second inputs and an output, said output being coupled to said data input of said first group of shift registers, and said first and second inputs being coupled to said second input and said output of said input exclusive-OR logic gate, respectively.
Claim 5
Dependent Claim
75 words
A cyclic redundancy check circuit as recited in claim 2, wherein said set signal generator means comprises a first AND logic gate comprising first and second AND gate inputs and a first AND gate output, wherein said first AND gate output is coupled to said common set input, said first AND gate input is coupled to receive a master set signal, and said second AND gate input is coupled to receive a set test signal.
Claim 6
Dependent Claim
23 words
A cyclic redundancy check circuit as recited in claim 2, wherein said XOR signal selector means comprises a dual input AND logic gate.
Claim 7
Dependent Claim
21 words
A cyclic redundancy check circuit as recited in claim 2, wherein said XOR signal selector means comprises a dual input multiplexer.
Claim 8
Dependent Claim
22 words
A cyclic redundancy check circuit as recited in claim 2, wherein said input data signal selector means comprises a dual input multiplexer.
References Cited (Backward Citations)
US4809273A
Cited
US5062111A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-17 | 1996-05-18 | 1996-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-17 | 2000-05-18 | 2000-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-17 | 2004-05-18 | 2004-11-17 | $7700.00 | Window Closed / Lapsed |