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US5164918A
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US
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Integrated circuit
Assignee: Sharp Corp
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Filing: 1990-08-29
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Granted: 1992-11-17
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Expires: 2010-08-29
Abstract
Abstract An integrated circuit having a memory capable of being tested protects data stored in the memory from being read out of the integrated circuit during testing. Data input during memory testing is internally compared with data stored in the memory. The integrated circuit also outputs the accumulated comparison results. The output comparision result also may differ from the data in timing. An input unit includes an external terminal and a plurality of buffers for controlling data input and output to and from the integrated circuit.
Inventors
- 👤 Eiji Ogino
- 👤 Shigeki Imai
- 👤 Masahiko Wada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:19
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/52; G11C7/00; G11C7/24
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
143 words
An integrated circuit having a memory capable of being tested while simultaneously protecting and preventing data stored in the memory from being read out from the integrated circuit, said integrated circuit comprising: means for inputting data into said memory and outputting data stored in said memory from said integrated circuit, said inputting means having an external terminal and a plurality of temporary storage elements; means connected to said inputting means for controlling said inputting means so that said data is only input into said inputting means during a test of said memory; and means connected to said control means for comparing said data input through said inputting means with data stored in said memory during said test of said memory, said comparing means having a plurality of logic circuits, each of said logic circuits being composed of a plurality of logic circuit elements.
Claim 2
Dependent Claim
143 words
An integrated circuit having a memory capable of being tested while simultaneously protecting and preventing data stored in the memory from being read out from the integrated circuit, said integrated circuit comprising: means for inputting data into said memory and outputting data stored in said memory from said integrated circuit, said inputting means having an external terminal and a plurality of temporary storage elements; means connected to said inputting means for controlling said inputting means so that said data is only input into said inputting means during a test of said memory; and means connected to said control means for comparing said data input through said inputting means with data stored in said memory during said test of said memory, said comparing means having a plurality of logic circuits, each of said logic circuits being composed of a plurality of logic circuit elements.
Claim 3
Dependent Claim
71 words
An integrated circuit according to claim 1, wherein said plurality of temporary storage elements include two buffers for respectively controlling an input and an output of said integrated circuit, one of said buffers being adapted to input data from said external terminal into said integrated circuit, the other one of said buffers being adapted to output data from said integrated circuit to said external terminal in accordance with a control signal.
Claim 4
Dependent Claim
35 words
An integrated circuit according to claim 2, wherein said control signal has two different states in accordance with states of said buffer, said states of said buffer being either an input or an output state.
Claim 5
Dependent Claim
100 words
An integrated circuit according to claim 1, wherein said plurality of logic circuit elements include an AND gate having a plurality of input terminals and an output terminals and an output terminal, a NOR gate having a plurality of input terminals and an output terminal, and an OR gate having a plurality of input terminals and an output terminal, one of said input terminals of said OR gate being connected to said output terminal of said AND gate and the another one of said input terminals of said OR gate being connected to said output terminal of said NOR gate.
Claim 6
Dependent Claim
52 words
An integrated circuit according to claim 4, wherein said comparing means further comprises a NAND gate having a plurality of input terminals and an output terminal, each of said plurality of input terminals being connected to each of said output terminals of said OR gates forming said plurality of logic circuits, respectively.
Claim 7
Dependent Claim
29 words
An integrated circuit according to claim 5, wherein said comparing means includes a comparator which is capable of outputting a signal representing a comparison result in a test mode.
Claim 8
Dependent Claim
36 words
An integrated circuit according to claim 6, wherein said integrated circuit further comprises an output control means connected to said comparing means for causing said comparison result to be output only once at a predetermined time.
Claim 9
Dependent Claim
19 words
An integrated circuit according to claim 7, wherein said output control means includes a plurality of serially connected flip-flops.
Claim 10
Dependent Claim
24 words
An integrated circuit according to claim 8, wherein the number of said plurality of flip-flops corresponds to the data storage capacity of said memory.
Claim 11
Dependent Claim
48 words
An integrated circuit according to claim 8, wherein one of said plurality of flip-flops is capable of accepting said comparison result output from said comparing means, and another one of said plurality of flip-flops is capable of outputting a signal only at a time of testing said memory.
Claim 12
Dependent Claim
49 words
An integrated circuit according to claim 10, wherein each of said plurality of flip-flops has an input terminal which receives a clock signal, and said comparison result output from said comparing means is supplied to said input terminal so that no additional clock signal is required to be input.
Claim 13
Dependent Claim
18 words
An integrated circuit according to claim 10, wherein said comparing means is capable of comparing all memory data.
References Cited (Backward Citations)
US4905142A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-17 | 1996-05-18 | 1996-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-17 | 2000-05-18 | 2000-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-17 | 2004-05-18 | 2004-11-17 | $7700.00 | Window Closed / Lapsed |