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US5164727A
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Optimal decoding method and apparatus for data acquisition applications of sigma delta modulators
Assignee: University of California
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Filing: 1991-04-30
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Granted: 1992-11-17
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Expires: 2011-04-30
Abstract
Abstract A class of optimal nonlinear decoding algorithms for data acquisition applications of Sigma Delta modulators is applicable to all current Sigma Delta structures, including single and double loop, cascade and interpolative modulators. The decoding method takes on a particularly simple form for the case of constant modular inputs. While the performance of the present invention is identical to other optimal nonlinear decoding schemes such as table look-up, the present invention is simpler to implement. Numerical results show that the performance of the invention exceed that of conventional linear decoding.
Inventors
- 👤 Avideh Zakhor
- 👤 Soren Hein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 17:47
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/30; H03M3/458; H03M3/476
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
109 words
In a data acquisition device having a Sigma Delta modulator with an unknown constant analog input and a N-bit binary digital output signal, decoding apparatus comprising means for converting said binary digital output signal into a digital approximation of said analog input signal, first and second register means for storing data corresponding to upper and lower bounds of said unknown constant analog input signal, means for calculating the upper or lower bound of said constant analog signal for each of said N bits and for updating said register means accordingly, and means for outputting the average of said register means as the digital approximation of said analog input signal.
Claim 2
Dependent Claim
109 words
In a data acquisition device having a Sigma Delta modulator with an unknown constant analog input and a N-bit binary digital output signal, decoding apparatus comprising means for converting said binary digital output signal into a digital approximation of said analog input signal, first and second register means for storing data corresponding to upper and lower bounds of said unknown constant analog input signal, means for calculating the upper or lower bound of said constant analog signal for each of said N bits and for updating said register means accordingly, and means for outputting the average of said register means as the digital approximation of said analog input signal.
Claim 3
Dependent Claim
14 words
The apparatus as in claim 1 wherein said modulator is a single loop modulator.
Claim 4
Dependent Claim
14 words
The apparatus as in claim 1 wherein said modulator is a double loop modulator.
Claim 5
Dependent Claim
13 words
The apparatus as in claim 1 wherein said modulator is a multi-stage modulator.
Claim 6
Dependent Claim
13 words
The apparatus as in claim 1 where said modulator is an interpolative modulator.
Claim 7
Dependent Claim
160 words
In a data acquisition device having a Sigma Delta modulator with an unknown time varying N-sample analog input signal and an N-bit binary digital output signal, apparatus for converting said binary digital output signal into a digital approximation of said analog input signal, said apparatus comprising N register means, means for maintaining said N register means corresponding to estimates of each of said N analog input samples, means for storing said N-bit digital output signal as an initial estimate stored in said register means, means for iteratively improving upon the estimate stored in said register means by alternating between two operations, namely one operation in which the current estimate stored in said register means is band-limited and subsequently stored in said register means, and the other operation in which the current estimate stored in said register means is modified to satisfy bounds so that the estimate generates said N-bit binary digital output signal as applied to said Sigma Delta modulator.
Claim 8
Dependent Claim
160 words
In a data acquisition device having a Sigma Delta modulator with an unknown time varying N-sample analog input signal and an N-bit binary digital output signal, apparatus for converting said binary digital output signal into a digital approximation of said analog input signal, said apparatus comprising N register means, means for maintaining said N register means corresponding to estimates of each of said N analog input samples, means for storing said N-bit digital output signal as an initial estimate stored in said register means, means for iteratively improving upon the estimate stored in said register means by alternating between two operations, namely one operation in which the current estimate stored in said register means is band-limited and subsequently stored in said register means, and the other operation in which the current estimate stored in said register means is modified to satisfy bounds so that the estimate generates said N-bit binary digital output signal as applied to said Sigma Delta modulator.
Claim 9
Dependent Claim
14 words
The apparatus as in claim 6 wherein said modulator is a single loop modulator.
Claim 10
Dependent Claim
14 words
The apparatus as in claim 6 wherein said modulator is a double loop modulator.
Claim 11
Dependent Claim
13 words
The apparatus as in claim 6 wherein said modulator is a multi-stage modulator.
Claim 12
Dependent Claim
13 words
The apparatus as in claim 6 where said modulator is an interpolative modulator.
Claim 13
Dependent Claim
109 words
In a data acquisition device having a Sigma Delta modulator with an unknown constant analog input and an N-bit binary digital output signal and first and second registers, the method comprising the steps of converting said binary digital output signal into a digital approximation of said analog input signal, storing in said first and second register data corresponding to upper and lower bounds of said unknown constant analog input signal, calculating the upper or lower bound of said constant analog signal for each of said N bits and updating said register means accordingly, and outputting the average of said registers as the digital approximation of said analog input signal.
Claim 14
Dependent Claim
109 words
In a data acquisition device having a Sigma Delta modulator with an unknown constant analog input and an N-bit binary digital output signal and first and second registers, the method comprising the steps of converting said binary digital output signal into a digital approximation of said analog input signal, storing in said first and second register data corresponding to upper and lower bounds of said unknown constant analog input signal, calculating the upper or lower bound of said constant analog signal for each of said N bits and updating said register means accordingly, and outputting the average of said registers as the digital approximation of said analog input signal.
Claim 15
Dependent Claim
150 words
In a data acquisition device having a Sigma Delta modulator with an unknown time vary N-sample analog input signal, an N-bit binary digital output signal and N registers, a method for converting said binary digital output signal into a digital approximation of said analog input signal, comprising the steps of maintaining said N register corresponding to estimates of each of said N analog input samples, storing said N-bit digital output signal as an initial estimate stored in said register means, iteratively improving upon the estimate stored in said registers by alternating between two operations, namely one operation in which the current estimate stored in said registers is band-limited and subsequently stored in said registers, and one operation in which the current estimate stored in said register means is modified to satisfy founds so that the estimate generates said N-bit binary digital output signal as applied to said Sigma Delta modulator.
Claim 16
Dependent Claim
150 words
In a data acquisition device having a Sigma Delta modulator with an unknown time vary N-sample analog input signal, an N-bit binary digital output signal and N registers, a method for converting said binary digital output signal into a digital approximation of said analog input signal, comprising the steps of maintaining said N register corresponding to estimates of each of said N analog input samples, storing said N-bit digital output signal as an initial estimate stored in said register means, iteratively improving upon the estimate stored in said registers by alternating between two operations, namely one operation in which the current estimate stored in said registers is band-limited and subsequently stored in said registers, and one operation in which the current estimate stored in said register means is modified to satisfy founds so that the estimate generates said N-bit binary digital output signal as applied to said Sigma Delta modulator.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-11-17 | 1996-05-18 | 1996-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-11-17 | 2000-05-18 | 2000-11-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-11-17 | 2004-05-18 | 2004-11-17 | $7700.00 | Window Closed / Lapsed |